Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Improved comments about memory read paths

Browse Source
This commit is contained in:
David Harris 2023-11-01 07:00:17 -07:00
parent 6f021aac54
commit c639f92d27
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/generic/mem/ram1p1rwbe.sv
View File

@ -90,12 +90,12 @@ module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=
end end
end end
// Read // Combinational read: register address and read after clock edge
logic [$clog2(DEPTH)-1:0] addrd; logic [$clog2(DEPTH)-1:0] addrd;
flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd); flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
assign dout = RAM[addrd]; assign dout = RAM[addrd];
/* // Read /* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q
always_ff @(posedge clk) always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */ if(ce) dout <= #1 mem[addr]; */

4
src/generic/mem/ram1p1rwe.sv
View File

@ -71,12 +71,12 @@ module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
// The version with byte write enables it correctly infers block ram. // The version with byte write enables it correctly infers block ram.
integer i; integer i;
// Read // Combinational read: register address and read after clock edge
logic [$clog2(DEPTH)-1:0] addrd; logic [$clog2(DEPTH)-1:0] addrd;
flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd); flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
assign dout = RAM[addrd]; assign dout = RAM[addrd];
/* // Read /* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q
always_ff @(posedge clk) always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */ if(ce) dout <= #1 mem[addr]; */