diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index 04e9eae3e..46716aa75 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -90,12 +90,12 @@ module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=
       end
     end
     
-    // Read
+    // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
     assign dout = RAM[addrd];
 
-    /*      // Read
+    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */
 
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
index 24d92ff7f..40929544a 100644
--- a/src/generic/mem/ram1p1rwe.sv
+++ b/src/generic/mem/ram1p1rwe.sv
@@ -71,12 +71,12 @@ module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
     // The version with byte write enables it correctly infers block ram.
     integer i;
 
-    // Read
+    // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
     assign dout = RAM[addrd];
 
-    /*      // Read
+    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */