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DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst

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David Harris 2023-11-12 20:23:27 -08:00
parent 065f3f3f6d
commit c44ae93e22
1 changed files with 1 additions and 2 deletions
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src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -86,8 +86,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
////////////////////////// //////////////////////////
// If the result is not exact, the sticky should be set // If the result is not exact, the sticky should be set
// assign DivStickyM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide assign DivStickyM = ~WZeroM & ~SpecialCaseM;
assign DivStickyM = ~WZeroM & ~(SpecialCaseM);
// Determine if sticky bit is negative // Determine if sticky bit is negative
assign Sum = WC + WS; assign Sum = WC + WS;