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fixed no forcing bug in linux testbench.

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This commit is contained in:
Ross Thompson 2022-04-17 17:49:51 -05:00
parent 238cc9f9fd
commit c409bde6ae
1 changed files with 4 additions and 3 deletions
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7
pipelined/testbench/testbench-linux.sv
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@ -27,7 +27,7 @@
`include "wally-config.vh" `include "wally-config.vh"
`define DEBUG_TRACE 2 `define DEBUG_TRACE 0
// Debug Levels // Debug Levels
// 0: don't check against QEMU // 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements // 1: print disagreements with QEMU, but only halt on PCW disagreements
@ -547,9 +547,10 @@ module testbench;
if(`"STAGE`"=="M") begin \ if(`"STAGE`"=="M") begin \
// override on special conditions \ // override on special conditions \
if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \ if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \
$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \ if(!NO_IE_MTIME_CHECKPOINT) begin \
if(!NO_IE_MTIME_CHECKPOINT) \ $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
end \
end else \ end else \
if(!NO_IE_MTIME_CHECKPOINT) \ if(!NO_IE_MTIME_CHECKPOINT) \
release dut.core.ieu.dp.ReadDataM; \ release dut.core.ieu.dp.ReadDataM; \