From c409bde6aee32047568491127099e485ae6a6d06 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 17 Apr 2022 17:49:51 -0500 Subject: [PATCH] fixed no forcing bug in linux testbench. --- pipelined/testbench/testbench-linux.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index f00ca8257..6f0cdf372 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ `include "wally-config.vh" -`define DEBUG_TRACE 2 +`define DEBUG_TRACE 0 // Debug Levels // 0: don't check against QEMU // 1: print disagreements with QEMU, but only halt on PCW disagreements @@ -547,9 +547,10 @@ module testbench; if(`"STAGE`"=="M") begin \ // override on special conditions \ if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \ - $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \ - if(!NO_IE_MTIME_CHECKPOINT) \ + if(!NO_IE_MTIME_CHECKPOINT) begin \ + $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \ force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ + end \ end else \ if(!NO_IE_MTIME_CHECKPOINT) \ release dut.core.ieu.dp.ReadDataM; \