diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc index 9059dc7f1..716136eca 100644 --- a/fpga/constraints/constraints.xdc +++ b/fpga/constraints/constraints.xdc @@ -282,7 +282,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] -set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 +set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] diff --git a/fpga/constraints/debug.xdc b/fpga/constraints/debug.xdc index cd1b265d8..9227ba6f6 100644 --- a/fpga/constraints/debug.xdc +++ b/fpga/constraints/debug.xdc @@ -1,26 +1,17 @@ ##### debugger ##### +connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]] - - - - - -connect_debug_port u_ila_0/probe34 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] -connect_debug_port u_ila_0/probe69 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]] -connect_debug_port u_ila_0/probe70 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]] - - - - -connect_debug_port u_ila_0/probe17 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]] -connect_debug_port u_ila_0/probe37 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]] -connect_debug_port u_ila_0/probe46 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]] -connect_debug_port u_ila_0/probe75 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]] -connect_debug_port u_ila_0/probe82 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]] -connect_debug_port u_ila_0/probe83 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]] -connect_debug_port u_ila_0/probe89 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]] -connect_debug_port u_ila_0/probe90 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]] +connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]] +connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]] +connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]] +connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]] +connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]] +connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]] +connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] @@ -35,291 +26,291 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list wrapper_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 12 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 4 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 4 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 4 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 6 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 64 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 64 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} 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{wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 64 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list 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{wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} 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{wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 6 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 64 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 6 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 64 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 6 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]] +connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 64 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 3 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 63 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 3 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 64 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[63]}]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/ReadDataM[0]} {wallypipelinedsoc/hart/ReadDataM[1]} {wallypipelinedsoc/hart/ReadDataM[2]} {wallypipelinedsoc/hart/ReadDataM[3]} {wallypipelinedsoc/hart/ReadDataM[4]} {wallypipelinedsoc/hart/ReadDataM[5]} {wallypipelinedsoc/hart/ReadDataM[6]} {wallypipelinedsoc/hart/ReadDataM[7]} {wallypipelinedsoc/hart/ReadDataM[8]} {wallypipelinedsoc/hart/ReadDataM[9]} {wallypipelinedsoc/hart/ReadDataM[10]} {wallypipelinedsoc/hart/ReadDataM[11]} {wallypipelinedsoc/hart/ReadDataM[12]} {wallypipelinedsoc/hart/ReadDataM[13]} {wallypipelinedsoc/hart/ReadDataM[14]} {wallypipelinedsoc/hart/ReadDataM[15]} {wallypipelinedsoc/hart/ReadDataM[16]} {wallypipelinedsoc/hart/ReadDataM[17]} {wallypipelinedsoc/hart/ReadDataM[18]} {wallypipelinedsoc/hart/ReadDataM[19]} {wallypipelinedsoc/hart/ReadDataM[20]} {wallypipelinedsoc/hart/ReadDataM[21]} {wallypipelinedsoc/hart/ReadDataM[22]} {wallypipelinedsoc/hart/ReadDataM[23]} {wallypipelinedsoc/hart/ReadDataM[24]} {wallypipelinedsoc/hart/ReadDataM[25]} {wallypipelinedsoc/hart/ReadDataM[26]} {wallypipelinedsoc/hart/ReadDataM[27]} {wallypipelinedsoc/hart/ReadDataM[28]} {wallypipelinedsoc/hart/ReadDataM[29]} {wallypipelinedsoc/hart/ReadDataM[30]} {wallypipelinedsoc/hart/ReadDataM[31]} {wallypipelinedsoc/hart/ReadDataM[32]} {wallypipelinedsoc/hart/ReadDataM[33]} {wallypipelinedsoc/hart/ReadDataM[34]} {wallypipelinedsoc/hart/ReadDataM[35]} {wallypipelinedsoc/hart/ReadDataM[36]} {wallypipelinedsoc/hart/ReadDataM[37]} {wallypipelinedsoc/hart/ReadDataM[38]} {wallypipelinedsoc/hart/ReadDataM[39]} {wallypipelinedsoc/hart/ReadDataM[40]} {wallypipelinedsoc/hart/ReadDataM[41]} {wallypipelinedsoc/hart/ReadDataM[42]} {wallypipelinedsoc/hart/ReadDataM[43]} {wallypipelinedsoc/hart/ReadDataM[44]} {wallypipelinedsoc/hart/ReadDataM[45]} {wallypipelinedsoc/hart/ReadDataM[46]} {wallypipelinedsoc/hart/ReadDataM[47]} {wallypipelinedsoc/hart/ReadDataM[48]} {wallypipelinedsoc/hart/ReadDataM[49]} {wallypipelinedsoc/hart/ReadDataM[50]} {wallypipelinedsoc/hart/ReadDataM[51]} {wallypipelinedsoc/hart/ReadDataM[52]} {wallypipelinedsoc/hart/ReadDataM[53]} {wallypipelinedsoc/hart/ReadDataM[54]} {wallypipelinedsoc/hart/ReadDataM[55]} {wallypipelinedsoc/hart/ReadDataM[56]} {wallypipelinedsoc/hart/ReadDataM[57]} {wallypipelinedsoc/hart/ReadDataM[58]} {wallypipelinedsoc/hart/ReadDataM[59]} {wallypipelinedsoc/hart/ReadDataM[60]} {wallypipelinedsoc/hart/ReadDataM[61]} {wallypipelinedsoc/hart/ReadDataM[62]} {wallypipelinedsoc/hart/ReadDataM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 64 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[63]}]] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/WriteDataM[0]} {wallypipelinedsoc/hart/WriteDataM[1]} {wallypipelinedsoc/hart/WriteDataM[2]} {wallypipelinedsoc/hart/WriteDataM[3]} {wallypipelinedsoc/hart/WriteDataM[4]} {wallypipelinedsoc/hart/WriteDataM[5]} {wallypipelinedsoc/hart/WriteDataM[6]} {wallypipelinedsoc/hart/WriteDataM[7]} {wallypipelinedsoc/hart/WriteDataM[8]} {wallypipelinedsoc/hart/WriteDataM[9]} {wallypipelinedsoc/hart/WriteDataM[10]} {wallypipelinedsoc/hart/WriteDataM[11]} {wallypipelinedsoc/hart/WriteDataM[12]} {wallypipelinedsoc/hart/WriteDataM[13]} {wallypipelinedsoc/hart/WriteDataM[14]} {wallypipelinedsoc/hart/WriteDataM[15]} {wallypipelinedsoc/hart/WriteDataM[16]} {wallypipelinedsoc/hart/WriteDataM[17]} {wallypipelinedsoc/hart/WriteDataM[18]} {wallypipelinedsoc/hart/WriteDataM[19]} {wallypipelinedsoc/hart/WriteDataM[20]} {wallypipelinedsoc/hart/WriteDataM[21]} {wallypipelinedsoc/hart/WriteDataM[22]} {wallypipelinedsoc/hart/WriteDataM[23]} {wallypipelinedsoc/hart/WriteDataM[24]} {wallypipelinedsoc/hart/WriteDataM[25]} {wallypipelinedsoc/hart/WriteDataM[26]} {wallypipelinedsoc/hart/WriteDataM[27]} {wallypipelinedsoc/hart/WriteDataM[28]} {wallypipelinedsoc/hart/WriteDataM[29]} {wallypipelinedsoc/hart/WriteDataM[30]} {wallypipelinedsoc/hart/WriteDataM[31]} {wallypipelinedsoc/hart/WriteDataM[32]} {wallypipelinedsoc/hart/WriteDataM[33]} {wallypipelinedsoc/hart/WriteDataM[34]} {wallypipelinedsoc/hart/WriteDataM[35]} {wallypipelinedsoc/hart/WriteDataM[36]} {wallypipelinedsoc/hart/WriteDataM[37]} {wallypipelinedsoc/hart/WriteDataM[38]} {wallypipelinedsoc/hart/WriteDataM[39]} {wallypipelinedsoc/hart/WriteDataM[40]} {wallypipelinedsoc/hart/WriteDataM[41]} {wallypipelinedsoc/hart/WriteDataM[42]} {wallypipelinedsoc/hart/WriteDataM[43]} {wallypipelinedsoc/hart/WriteDataM[44]} {wallypipelinedsoc/hart/WriteDataM[45]} {wallypipelinedsoc/hart/WriteDataM[46]} {wallypipelinedsoc/hart/WriteDataM[47]} {wallypipelinedsoc/hart/WriteDataM[48]} {wallypipelinedsoc/hart/WriteDataM[49]} {wallypipelinedsoc/hart/WriteDataM[50]} {wallypipelinedsoc/hart/WriteDataM[51]} {wallypipelinedsoc/hart/WriteDataM[52]} {wallypipelinedsoc/hart/WriteDataM[53]} {wallypipelinedsoc/hart/WriteDataM[54]} {wallypipelinedsoc/hart/WriteDataM[55]} {wallypipelinedsoc/hart/WriteDataM[56]} {wallypipelinedsoc/hart/WriteDataM[57]} {wallypipelinedsoc/hart/WriteDataM[58]} {wallypipelinedsoc/hart/WriteDataM[59]} {wallypipelinedsoc/hart/WriteDataM[60]} {wallypipelinedsoc/hart/WriteDataM[61]} {wallypipelinedsoc/hart/WriteDataM[62]} {wallypipelinedsoc/hart/WriteDataM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 3 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 5 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 4 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 4 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 64 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 64 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 32 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 2 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 32 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 64 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[63]}]] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 64 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[63]}]] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 2 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemRWM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemRWM[1]}]] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/hart/MemRWM[0]} {wallypipelinedsoc/hart/MemRWM[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 32 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[31]}]] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/InstrM[0]} {wallypipelinedsoc/hart/InstrM[1]} {wallypipelinedsoc/hart/InstrM[2]} {wallypipelinedsoc/hart/InstrM[3]} {wallypipelinedsoc/hart/InstrM[4]} {wallypipelinedsoc/hart/InstrM[5]} {wallypipelinedsoc/hart/InstrM[6]} {wallypipelinedsoc/hart/InstrM[7]} {wallypipelinedsoc/hart/InstrM[8]} {wallypipelinedsoc/hart/InstrM[9]} {wallypipelinedsoc/hart/InstrM[10]} {wallypipelinedsoc/hart/InstrM[11]} {wallypipelinedsoc/hart/InstrM[12]} {wallypipelinedsoc/hart/InstrM[13]} {wallypipelinedsoc/hart/InstrM[14]} {wallypipelinedsoc/hart/InstrM[15]} {wallypipelinedsoc/hart/InstrM[16]} {wallypipelinedsoc/hart/InstrM[17]} {wallypipelinedsoc/hart/InstrM[18]} {wallypipelinedsoc/hart/InstrM[19]} {wallypipelinedsoc/hart/InstrM[20]} {wallypipelinedsoc/hart/InstrM[21]} {wallypipelinedsoc/hart/InstrM[22]} {wallypipelinedsoc/hart/InstrM[23]} {wallypipelinedsoc/hart/InstrM[24]} {wallypipelinedsoc/hart/InstrM[25]} {wallypipelinedsoc/hart/InstrM[26]} {wallypipelinedsoc/hart/InstrM[27]} {wallypipelinedsoc/hart/InstrM[28]} {wallypipelinedsoc/hart/InstrM[29]} {wallypipelinedsoc/hart/InstrM[30]} {wallypipelinedsoc/hart/InstrM[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBAck]] +connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBAck]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBRead]] +connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBRead]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBWrite]] +connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBWrite]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]] +connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/EcallFaultM]] +connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/hart/priv/trap/EcallFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]] +connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]] +connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]] +connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]] +connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]] +connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]] +connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]] +connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrValidM]] +connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/InstrValidM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] set_property port_width 1 [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]] +connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] set_property port_width 1 [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]] +connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] set_property port_width 1 [get_debug_ports u_ila_0/probe47] -connect_debug_port u_ila_0/probe47 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]] +connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] set_property port_width 1 [get_debug_ports u_ila_0/probe48] -connect_debug_port u_ila_0/probe48 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/mretM]] +connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv/trap/mretM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] set_property port_width 1 [get_debug_ports u_ila_0/probe49] -connect_debug_port u_ila_0/probe49 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]] +connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] set_property port_width 1 [get_debug_ports u_ila_0/probe50] -connect_debug_port u_ila_0/probe50 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]] +connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] set_property port_width 1 [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]] +connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] set_property port_width 1 [get_debug_ports u_ila_0/probe52] -connect_debug_port u_ila_0/probe52 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]] +connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] set_property port_width 1 [get_debug_ports u_ila_0/probe53] -connect_debug_port u_ila_0/probe53 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]] +connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] set_property port_width 1 [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] set_property port_width 1 [get_debug_ports u_ila_0/probe55] -connect_debug_port u_ila_0/probe55 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/sretM]] +connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/hart/priv/trap/sretM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] set_property port_width 1 [get_debug_ports u_ila_0/probe56] -connect_debug_port u_ila_0/probe56 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]] +connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] set_property port_width 1 [get_debug_ports u_ila_0/probe57] -connect_debug_port u_ila_0/probe57 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]] +connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] set_property port_width 1 [get_debug_ports u_ila_0/probe58] -connect_debug_port u_ila_0/probe58 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StorePageFaultM]] +connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/hart/priv/trap/StorePageFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] set_property port_width 1 [get_debug_ports u_ila_0/probe59] -connect_debug_port u_ila_0/probe59 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/TrapM]] +connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/hart/TrapM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] set_property port_width 1 [get_debug_ports u_ila_0/probe60] -connect_debug_port u_ila_0/probe60 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]] +connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] set_property port_width 1 [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] set_property port_width 1 [get_debug_ports u_ila_0/probe62] -connect_debug_port u_ila_0/probe62 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]] +connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] set_property port_width 1 [get_debug_ports u_ila_0/probe63] -connect_debug_port u_ila_0/probe63 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/DTRb]] +connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/uncore/uart.uart/DTRb]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] set_property port_width 1 [get_debug_ports u_ila_0/probe64] -connect_debug_port u_ila_0/probe64 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/INTR]] +connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/uncore/uart.uart/INTR]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] set_property port_width 1 [get_debug_ports u_ila_0/probe65] -connect_debug_port u_ila_0/probe65 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/OUT1b]] +connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT1b]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] set_property port_width 1 [get_debug_ports u_ila_0/probe66] -connect_debug_port u_ila_0/probe66 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/OUT2b]] +connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT2b]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] set_property port_width 1 [get_debug_ports u_ila_0/probe67] -connect_debug_port u_ila_0/probe67 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/RTSb]] +connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RTSb]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] set_property port_width 1 [get_debug_ports u_ila_0/probe68] -connect_debug_port u_ila_0/probe68 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/RXRDYb]] +connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RXRDYb]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] set_property port_width 1 [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/SIN]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SIN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] set_property port_width 1 [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/SOUT]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SOUT]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] set_property port_width 1 [get_debug_ports u_ila_0/probe71] -connect_debug_port u_ila_0/probe71 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/TXRDYb]] +connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore/uart.uart/TXRDYb]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index affeb45bd..38dc7dce8 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -130,6 +130,8 @@ report_utilization -hierarchical -file re report_cdc -file reports/cdc.rpt report_clock_interaction -file reports/clock_interaction.rpt +source ../constraints/debug2.xdc + # set for RuntimeOptimized implementation #set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 0ebededc9..3bb2eb0cf 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -51,7 +51,6 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( initial begin //$readmemh(PRELOAD, RAM); -/* -----\/----- EXCLUDED -----\/----- // FPGA only RAM[0] = 64'h94e1819300002197; RAM[1] = 64'h4281420141014081; @@ -95,7 +94,6 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( RAM[39] = 64'h1047278367498082; RAM[40] = 64'h67c98082dfed8b85; RAM[41] = 64'h0000808210a7a023; - -----/\----- EXCLUDED -----/\----- */ end assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);