Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.

Browse Source
This commit is contained in:
Ross Thompson 2021-07-15 11:00:42 -05:00
parent c954fb510b
commit c39a228266
3 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
wally-pipelined/src/cache/dcache.sv vendored
View File

@ -434,6 +434,13 @@ module dcache
STATE_READY: begin STATE_READY: begin
// TLB Miss // TLB Miss
if(AnyCPUReqM & DTLBMissM) begin if(AnyCPUReqM & DTLBMissM) begin
// the LSU arbiter has not yet selected the PTW.
// The CPU needs to be stalled until that happens.
// If we set DCacheStall for 1 cycle before going to
// PTW ready the CPU will stall.
// The page table walker asserts it's control 1 cycle
// after the TLBs miss.
DCacheStall = 1'b1;
NextState = STATE_PTW_READY; NextState = STATE_PTW_READY;
end end
// amo hit // amo hit
@ -580,6 +587,7 @@ module dcache
end end
STATE_PTW_READY: begin STATE_PTW_READY: begin
// now all output connect to PTW instead of CPU.
CommittedM = 1'b1; CommittedM = 1'b1;
// return to ready if page table walk completed. // return to ready if page table walk completed.
if(DTLBWriteM) begin if(DTLBWriteM) begin

10
wally-pipelined/src/mmu/pagetablewalker.sv
View File

@ -77,7 +77,6 @@ module pagetablewalker
if (`MEM_VIRTMEM) begin if (`MEM_VIRTMEM) begin
// Internal signals // Internal signals
// register TLBs translation miss requests // register TLBs translation miss requests
logic [`XLEN-1:0] TranslationVAdrQ;
logic ITLBMissFQ, DTLBMissMQ; logic ITLBMissFQ, DTLBMissMQ;
logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] BasePageTablePPN;
@ -138,13 +137,6 @@ module pagetablewalker
assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr
assign SelDataTranslation = DTLBMissMQ | DTLBMissM; assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
flopenr #(`XLEN)
TranslationVAdrReg(.clk(clk),
.reset(reset),
.en(StartWalk),
.d(TranslationVAdr),
.q(TranslationVAdrQ));
flopenrc #(1) flopenrc #(1)
DTLBMissMReg(.clk(clk), DTLBMissMReg(.clk(clk),
.reset(reset), .reset(reset),
@ -170,7 +162,7 @@ module pagetablewalker
(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
(WalkerState == FAULT); (WalkerState == FAULT);
assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ);
//assign HPTWTranslate = DTLBMissM | ITLBMissF; //assign HPTWTranslate = DTLBMissM | ITLBMissF;
// unswizzle PTE bits // unswizzle PTE bits

2
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -543,10 +543,10 @@ string tests32f[] = '{
if (`C_SUPPORTED) tests = {tests, tests64ic}; if (`C_SUPPORTED) tests = {tests, tests64ic};
else tests = {tests, tests64iNOc}; else tests = {tests, tests64iNOc};
if (`M_SUPPORTED) tests = {tests, tests64m}; if (`M_SUPPORTED) tests = {tests, tests64m};
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
//if (`A_SUPPORTED) tests = {tests, tests64a}; //if (`A_SUPPORTED) tests = {tests, tests64a};
if (`F_SUPPORTED) tests = {tests64f, tests}; if (`F_SUPPORTED) tests = {tests64f, tests};
if (`D_SUPPORTED) tests = {tests64d, tests}; if (`D_SUPPORTED) tests = {tests64d, tests};
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
end end
//tests = {tests64a, tests}; //tests = {tests64a, tests};
end else begin // RV32 end else begin // RV32