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sram1rw cleanup

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This commit is contained in:
David Harris 2022-02-03 18:03:22 +00:00
parent 0e1d784b60
commit c3122ce214
1 changed files with 3 additions and 2 deletions
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5
pipelined/src/cache/cachefsm.sv vendored
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@ -92,8 +92,8 @@ module cachefsm
STATE_MISS_READ_WORD_DELAY, STATE_MISS_READ_WORD_DELAY,
STATE_MISS_WRITE_WORD, STATE_MISS_WRITE_WORD,
STATE_CPU_BUSY, STATE_CPU_BUSY, // *** Ross will change
STATE_CPU_BUSY_FINISH_AMO, STATE_CPU_BUSY_FINISH_AMO, // *** Ross will change
STATE_FLUSH, STATE_FLUSH,
STATE_FLUSH_CHECK, STATE_FLUSH_CHECK,
@ -120,6 +120,7 @@ module cachefsm
else CurrState <= #1 NextState; else CurrState <= #1 NextState;
// next state logic and some state ouputs. // next state logic and some state ouputs.
// *** Ross simplify: factor out next state and output logic
always_comb begin always_comb begin
CacheStall = 1'b0; CacheStall = 1'b0;
PreSelAdr = 2'b00; PreSelAdr = 2'b00;