From c3122ce21408b63a4f4df3d4c65ee68c6a100335 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 3 Feb 2022 18:03:22 +0000
Subject: [PATCH] sram1rw cleanup

---
 pipelined/src/cache/cachefsm.sv | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index 7d4d2f77d..115107bcd 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -92,8 +92,8 @@ module cachefsm
 					   STATE_MISS_READ_WORD_DELAY,
 					   STATE_MISS_WRITE_WORD,
 
-					   STATE_CPU_BUSY,
-					   STATE_CPU_BUSY_FINISH_AMO,
+					   STATE_CPU_BUSY, // *** Ross will change
+					   STATE_CPU_BUSY_FINISH_AMO, // *** Ross will change
   
 					   STATE_FLUSH,
 					   STATE_FLUSH_CHECK,
@@ -120,6 +120,7 @@ module cachefsm
     else CurrState <= #1 NextState;  
   
   // next state logic and some state ouputs.
+  // *** Ross simplify: factor out next state and output logic
   always_comb begin
     CacheStall = 1'b0;
     PreSelAdr = 2'b00;