From c307cff503855f5dc5047a90b4f3bf1056e11e00 Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Thu, 7 Apr 2022 17:21:20 +0000
Subject: [PATCH] fixed errors and warnings in rv32e

---
 addins/riscv-arch-test      |  2 +-
 pipelined/src/fpu/fma.sv    | 16 ++++++++--------
 pipelined/src/fpu/unpack.sv |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index effd553a6..be67c99bd 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv
index 8d1ae344a..db8ecaf2f 100644
--- a/pipelined/src/fpu/fma.sv
+++ b/pipelined/src/fpu/fma.sv
@@ -193,7 +193,7 @@ module expadd(
             endcase
         end
 
-    end else begin
+    end else if (`FPSIZES == 4) begin
         always_comb begin
             case (FmtE)
                 2'h3: Denorm = 1;
@@ -619,7 +619,7 @@ module normalize(
             endcase
         end
 
-    end else begin
+    end else if (`FPSIZES == 4) begin
         always_comb begin
             case (FmtM)
                 2'h3: SumExpTmp = SumExpTmpTmp;
@@ -664,7 +664,7 @@ module normalize(
             endcase
         end
 
-    end else begin
+    end else if (`FPSIZES == 4) begin
         logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
         assign Sum0LEZ  = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
         assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF  )-(`NE+2)'(2));
@@ -719,7 +719,7 @@ module normalize(
         (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&((FmtM==`FMT1)|(FmtM==`FMT2))) | 
         (|CorrSumShifted[3*`NF+2-`NF2:3*`NF+3-`NF1]&(FmtM==`FMT2));
 
-    end else begin        
+    end else if (`FPSIZES == 4) begin        
         assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | 
         (|CorrSumShifted[3*`NF+2-`D_NF:2*`NF+3]&((FmtM==1)|(FmtM==0)|(FmtM==2))) | 
         (|CorrSumShifted[3*`NF+2-`S_NF:3*`NF+3-`D_NF]&((FmtM==0)|(FmtM==2))) |
@@ -876,7 +876,7 @@ module fmaround(
             endcase
         end
 
-    end else begin
+    end else if (`FPSIZES == 4) begin
         always_comb begin
             case (FmtM)
                 2'h3: begin
@@ -995,7 +995,7 @@ module fmaround(
             endcase
         end
 
-    end else begin        
+    end else if (`FPSIZES == 4) begin        
         always_comb begin
             case (FmtM)
                 2'h3: RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1};
@@ -1063,7 +1063,7 @@ module fmaflags(
             endcase
         end
 
-    end else begin        
+    end else if (`FPSIZES == 4) begin        
         always_comb begin
             case (FmtM)
                 2'h3: GtMaxExp =  &FullResultExp[`NE-1:0] | FullResultExp[`NE];
@@ -1223,7 +1223,7 @@ module resultselect(
             endcase
         end
 
-    end else begin 
+    end else if (`FPSIZES == 4) begin 
         always_comb begin
             case (FmtM)
                 2'h3: begin  
diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv
index 3041cd72f..1c0589e10 100644
--- a/pipelined/src/fpu/unpack.sv
+++ b/pipelined/src/fpu/unpack.sv
@@ -261,7 +261,7 @@ module unpack (
             endcase
         end
 
-    end else begin      // if all precsisons are supported - quad, double, single, and half
+    end else if (`FPSIZES == 4) begin      // if all precsisons are supported - quad, double, single, and half
     
         //    quad   |  double  |  single  |  half    
         //-------------------------------------------------------------------