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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2024-12-30 12:52:04 -08:00
commit c283633839
4 changed files with 47 additions and 47 deletions
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2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit efd70ce71a352eb8c4ca3d3b63d06a7b076078cb Subproject commit acf99b1df40b4c90090f17ce1448a7d6a6fde1f5

4
bin/regression-wally
View File

@ -33,7 +33,7 @@ tests = [
"arch32i", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
"arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb",
"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh", "arch32vm_sv32"]], # Add when working: arch32pmp
["rv64i", ["arch64i"]] ["rv64i", ["arch64i"]]
] ]
@ -60,7 +60,7 @@ tests64gc_nofp = [
["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv", "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv",
"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz" "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz", "arch64pmp"
] ]
tests64gc_fp = [ tests64gc_fp = [

82
testbench/tests.vh
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@ -196,47 +196,47 @@ string arch32pmp[] = '{
string arch64pmp[] = '{ string arch64pmp[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/pmp64/pmp64-CFG-reg.S", "rv64i_m/pmp64/src/pmp64-CFG-reg.S",
"rv64i_m/pmp64/pmp64-CSR-access.S", "rv64i_m/pmp64/src/pmp64-CSR-access.S",
"rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NA4-R-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-R-priority.S", "rv64i_m/pmp64/src/pmp64-NA4-R-priority.S",
"rv64i_m/pmp64/pmp64-NA4-R.S", "rv64i_m/pmp64/src/pmp64-NA4-R.S",
"rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NA4-RW-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-RW-priority.S", "rv64i_m/pmp64/src/pmp64-NA4-RW-priority.S",
"rv64i_m/pmp64/pmp64-NA4-RW.S", "rv64i_m/pmp64/src/pmp64-NA4-RW.S",
"rv64i_m/pmp64/pmp64-NA4-RWX.S", "rv64i_m/pmp64/src/pmp64-NA4-RWX.S",
"rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NA4-RX-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-RX-priority.S", "rv64i_m/pmp64/src/pmp64-NA4-RX-priority.S",
"rv64i_m/pmp64/pmp64-NA4-RX.S", "rv64i_m/pmp64/src/pmp64-NA4-RX.S",
"rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NA4-X-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-X-priority.S", "rv64i_m/pmp64/src/pmp64-NA4-X-priority.S",
"rv64i_m/pmp64/pmp64-NA4-X.S", "rv64i_m/pmp64/src/pmp64-NA4-X.S",
"rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NAPOT-R-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-R-priority.S", "rv64i_m/pmp64/src/pmp64-NAPOT-R-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-R.S", "rv64i_m/pmp64/src/pmp64-NAPOT-R.S",
"rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RW-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RW-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-RW.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RW.S",
"rv64i_m/pmp64/pmp64-NAPOT-RWX.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RWX.S",
"rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RX-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RX-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-RX.S", "rv64i_m/pmp64/src/pmp64-NAPOT-RX.S",
"rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-NAPOT-X-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-X-priority.S", "rv64i_m/pmp64/src/pmp64-NAPOT-X-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-X.S", "rv64i_m/pmp64/src/pmp64-NAPOT-X.S",
"rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-TOR-R-priority-level-2.S",
"rv64i_m/pmp64/pmp64-TOR-R-priority.S", "rv64i_m/pmp64/src/pmp64-TOR-R-priority.S",
"rv64i_m/pmp64/pmp64-TOR-R.S", "rv64i_m/pmp64/src/pmp64-TOR-R.S",
"rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S", "rv64i_m/pmp64/src/pmp64-TOR-RW-priority-level-2..S",
"rv64i_m/pmp64/pmp64-TOR-RW-priority.S", "rv64i_m/pmp64/src/pmp64-TOR-RW-priority.S",
"rv64i_m/pmp64/pmp64-TOR-RW.S", "rv64i_m/pmp64/src/pmp64-TOR-RW.S",
"rv64i_m/pmp64/pmp64-TOR-RWX.S", "rv64i_m/pmp64/src/pmp64-TOR-RWX.S",
"rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-TOR-RX-priority-level-2.S",
"rv64i_m/pmp64/pmp64-TOR-RX-priority.S", "rv64i_m/pmp64/src/pmp64-TOR-RX-priority.S",
"rv64i_m/pmp64/pmp64-TOR-RX.S", "rv64i_m/pmp64/src/pmp64-TOR-RX.S",
"rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S", "rv64i_m/pmp64/src/pmp64-TOR-X-priority-level-2.S",
"rv64i_m/pmp64/pmp64-TOR-X-priority.S", "rv64i_m/pmp64/src/pmp64-TOR-X-priority.S",
"rv64i_m/pmp64/pmp64-TOR-X.S" "rv64i_m/pmp64/src/pmp64-TOR-X.S"
}; };
string arch32vm_sv32[] = '{ string arch32vm_sv32[] = '{

6
tests/riscof/spike/spike_rv32gc_isa.yaml
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@ -1,12 +1,12 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
# ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh # ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 32 physical_addr_sz: 32
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [32] supported_xlen: [32]
misa: misa:
reset-val: 0x4000112D reset-val: 0x4014112D
rv32: rv32:
accessible: true accessible: true
mxl: mxl:
@ -24,6 +24,6 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- extensions[25:0] bitmask [0x000112D, 0x0000000] - extensions[25:0] bitmask [0x014112D, 0x0000000]
wr_illegal: wr_illegal:
- Unchanged - Unchanged