From fb642c7f35ba853bfb538e83a2c6c022abf342c6 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 23 Dec 2024 13:50:07 +0000 Subject: [PATCH 1/3] Bump addins/cvw-arch-verif from `efd70ce` to `f04bcd7` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `efd70ce` to `f04bcd7`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/efd70ce71a352eb8c4ca3d3b63d06a7b076078cb...f04bcd729f46d66ff42c31ee8112cd447a5aa0a3) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index efd70ce71..f04bcd729 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit efd70ce71a352eb8c4ca3d3b63d06a7b076078cb +Subproject commit f04bcd729f46d66ff42c31ee8112cd447a5aa0a3 From 5f68d6d58598c6e91eb15a3bd7e09ab077bea971 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 30 Dec 2024 13:26:46 +0000 Subject: [PATCH 2/3] Bump addins/cvw-arch-verif from `f04bcd7` to `acf99b1` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `f04bcd7` to `acf99b1`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/f04bcd729f46d66ff42c31ee8112cd447a5aa0a3...acf99b1df40b4c90090f17ce1448a7d6a6fde1f5) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index f04bcd729..acf99b1df 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit f04bcd729f46d66ff42c31ee8112cd447a5aa0a3 +Subproject commit acf99b1df40b4c90090f17ce1448a7d6a6fde1f5 From f890cc9fd6225c1a95cca8a88e0d399eddec3c06 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 30 Dec 2024 12:37:27 -0800 Subject: [PATCH 3/3] Enable riscv-arch-test vm sv32 tests in regression --- bin/regression-wally | 4 +- testbench/tests.vh | 82 ++++++++++++------------ tests/riscof/spike/spike_rv32gc_isa.yaml | 6 +- 3 files changed, 46 insertions(+), 46 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index c89e80dcd..f1abbd477 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -33,7 +33,7 @@ tests = [ "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb", - "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], + "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh", "arch32vm_sv32"]], # Add when working: arch32pmp ["rv64i", ["arch64i"]] ] @@ -60,7 +60,7 @@ tests64gc_nofp = [ ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz" + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz", "arch64pmp" ] tests64gc_fp = [ diff --git a/testbench/tests.vh b/testbench/tests.vh index 59cd84437..bff553a1f 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -196,47 +196,47 @@ string arch32pmp[] = '{ string arch64pmp[] = '{ `RISCVARCHTEST, - "rv64i_m/pmp64/pmp64-CFG-reg.S", - "rv64i_m/pmp64/pmp64-CSR-access.S", - "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-R-priority.S", - "rv64i_m/pmp64/pmp64-NA4-R.S", - "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-RW-priority.S", - "rv64i_m/pmp64/pmp64-NA4-RW.S", - "rv64i_m/pmp64/pmp64-NA4-RWX.S", - "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-RX-priority.S", - "rv64i_m/pmp64/pmp64-NA4-RX.S", - "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-X-priority.S", - "rv64i_m/pmp64/pmp64-NA4-X.S", - "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-R.S", - "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-RW.S", - "rv64i_m/pmp64/pmp64-NAPOT-RWX.S", - "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-RX.S", - "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-X.S", - "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S", - "rv64i_m/pmp64/pmp64-TOR-R-priority.S", - "rv64i_m/pmp64/pmp64-TOR-R.S", - "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S", - "rv64i_m/pmp64/pmp64-TOR-RW-priority.S", - "rv64i_m/pmp64/pmp64-TOR-RW.S", - "rv64i_m/pmp64/pmp64-TOR-RWX.S", - "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S", - "rv64i_m/pmp64/pmp64-TOR-RX-priority.S", - "rv64i_m/pmp64/pmp64-TOR-RX.S", - "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S", - "rv64i_m/pmp64/pmp64-TOR-X-priority.S", - "rv64i_m/pmp64/pmp64-TOR-X.S" + "rv64i_m/pmp64/src/pmp64-CFG-reg.S", + "rv64i_m/pmp64/src/pmp64-CSR-access.S", + "rv64i_m/pmp64/src/pmp64-NA4-R-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-R-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-R.S", + "rv64i_m/pmp64/src/pmp64-NA4-RW-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-RW-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-RW.S", + "rv64i_m/pmp64/src/pmp64-NA4-RWX.S", + "rv64i_m/pmp64/src/pmp64-NA4-RX-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-RX-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-RX.S", + "rv64i_m/pmp64/src/pmp64-NA4-X-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-X-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-X.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-R-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-R-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-R.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RW-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RW-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RW.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RWX.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RX-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RX-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RX.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-X-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-X-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-X.S", + "rv64i_m/pmp64/src/pmp64-TOR-R-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-TOR-R-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-R.S", + "rv64i_m/pmp64/src/pmp64-TOR-RW-priority-level-2..S", + "rv64i_m/pmp64/src/pmp64-TOR-RW-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-RW.S", + "rv64i_m/pmp64/src/pmp64-TOR-RWX.S", + "rv64i_m/pmp64/src/pmp64-TOR-RX-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-TOR-RX-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-RX.S", + "rv64i_m/pmp64/src/pmp64-TOR-X-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-TOR-X-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-X.S" }; string arch32vm_sv32[] = '{ diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 0b07212cc..281f58a7b 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: # ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x4000112D + reset-val: 0x4014112D rv32: accessible: true mxl: @@ -24,6 +24,6 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x000112D, 0x0000000] + - extensions[25:0] bitmask [0x014112D, 0x0000000] wr_illegal: - Unchanged \ No newline at end of file