Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed typo in fpga Makefile.

Browse Source
This commit is contained in:
Rose Thompson 2024-09-03 12:19:16 -07:00
parent 8248f2dd66
commit c24d061d0a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/generator/Makefile
View File

@ -15,14 +15,14 @@ vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
vcu118: export board := vcu118
vcu118: export SYSTEMCLOCK := 71000000
ArtyA7: export MAXSDCLOCK := 1000000
ArtyA7: export MAXSDCCLOCK := 1000000
vcu118: FPGA_VCU
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
vcu108: export board := vcu108
vcu108: export SYSTEMCLOCK := 50000000
ArtyA7: export MAXSDCLOCK := 12500000
ArtyA7: export MAXSDCCLOCK := 12500000
vcu108: FPGA_VCU
# variables computed from config