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https://github.com/openhwgroup/cvw
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Removed P.FPGA from testbench.
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c43377afff
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c1d6fddea8
@ -265,10 +265,8 @@ module testbench;
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
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// the addr of each label and fill the array. To expand, add more elements to this array
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// and initialize them to zero (also initilaize them to zero at the start of the next test)
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if(!P.FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Verify the test ran correctly by checking the memory against a known signature.
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@ -361,21 +359,21 @@ module testbench;
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////////////////////////////////////////////////////////////////////////////////
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// load memories with program image
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////////////////////////////////////////////////////////////////////////////////
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if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator
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if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED // this is a gross hack for xcelium and verilator
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if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
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if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
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if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
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always @(posedge clk) begin
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if (LoadMem) begin
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if (P.FPGA) begin
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`ifdef TB_FPGA
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if (P.SDC_SUPPORTED) begin
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`ifdef TB_SDC_SUPPORTED
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string romfilename, sdcfilename;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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// shorten sdc timers for simulation
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dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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`endif
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end
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else if (P.IROM_SUPPORTED) begin
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@ -37,9 +37,9 @@ module testbench;
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parameter DEBUG=0;
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parameter TEST="none";
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parameter PrintHPMCounters=1;
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parameter BPRED_LOGGER=0;
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parameter I_CACHE_ADDR_LOGGER=0;
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parameter D_CACHE_ADDR_LOGGER=0;
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parameter BPRED_LOGGER=1;
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parameter I_CACHE_ADDR_LOGGER=1;
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parameter D_CACHE_ADDR_LOGGER=1;
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`include "parameter-defs.vh"
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@ -260,10 +260,8 @@ module testbench;
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
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// the addr of each label and fill the array. To expand, add more elements to this array
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// and initialize them to zero (also initilaize them to zero at the start of the next test)
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if(!P.FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Verify the test ran correctly by checking the memory against a known signature.
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@ -344,14 +342,14 @@ module testbench;
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////////////////////////////////////////////////////////////////////////////////
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always @(posedge clk) begin
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if (LoadMem) begin
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if (P.FPGA) begin
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if (P.SDC_SUPPORTED) begin
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string romfilename, sdcfilename;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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// shorten sdc timers for simulation
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dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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end
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else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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@ -377,7 +375,7 @@ module testbench;
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assign {HRESPEXT, HRDATAEXT} = '0;
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end
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if(P.FPGA) begin : sdcard
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if(P.SDC_SUPPORTED) begin : sdcard
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// *** fix later
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/* -----\/----- EXCLUDED -----\/-----
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sdModel sdcard
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