diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv
index f50259ca8..89a7cc995 100644
--- a/testbench/testbench-xcelium.sv
+++ b/testbench/testbench-xcelium.sv
@@ -265,9 +265,7 @@ module testbench;
       // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
       // the addr of each label and fill the array. To expand, add more elements to this array 
       // and initialize them to zero (also initilaize them to zero at the start of the next test)
-      if(!P.FPGA) begin
-        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-      end
+      updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
     end
     
   ////////////////////////////////////////////////////////////////////////////////
@@ -361,21 +359,21 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
   // load memories with program image
   ////////////////////////////////////////////////////////////////////////////////
-  if (P.FPGA) `define TB_FPGA  // this is a gross hack for xcelium and verilator
+  if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED  // this is a gross hack for xcelium and verilator
   if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
   if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
   if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
   always @(posedge clk) begin
     if (LoadMem) begin
-      if (P.FPGA) begin
-      `ifdef TB_FPGA
+      if (P.SDC_SUPPORTED) begin
+      `ifdef TB_SDC_SUPPORTED
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
-        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // shorten sdc timers for simulation
-        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       `endif
       end
       else if (P.IROM_SUPPORTED) begin
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 74077e547..8635a4920 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -37,9 +37,9 @@ module testbench;
   parameter DEBUG=0;
   parameter TEST="none";
   parameter PrintHPMCounters=1;
-  parameter BPRED_LOGGER=0;
-  parameter I_CACHE_ADDR_LOGGER=0;
-  parameter D_CACHE_ADDR_LOGGER=0;
+  parameter BPRED_LOGGER=1;
+  parameter I_CACHE_ADDR_LOGGER=1;
+  parameter D_CACHE_ADDR_LOGGER=1;
  
 `include "parameter-defs.vh"
 
@@ -260,9 +260,7 @@ module testbench;
       // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
       // the addr of each label and fill the array. To expand, add more elements to this array 
       // and initialize them to zero (also initilaize them to zero at the start of the next test)
-      if(!P.FPGA) begin
-        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-      end
+      updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
     end
     
   ////////////////////////////////////////////////////////////////////////////////
@@ -344,14 +342,14 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
   always @(posedge clk) begin
     if (LoadMem) begin
-      if (P.FPGA) begin
+      if (P.SDC_SUPPORTED) begin
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
-        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // shorten sdc timers for simulation
-        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       end 
       else if (P.IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
       else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
@@ -377,7 +375,7 @@ module testbench;
     assign {HRESPEXT, HRDATAEXT} = '0;
   end
 
-  if(P.FPGA) begin : sdcard
+  if(P.SDC_SUPPORTED) begin : sdcard
     // *** fix later
 /* -----\/----- EXCLUDED -----\/-----
     sdModel sdcard
@@ -394,7 +392,7 @@ module testbench;
     assign SDCIntr = '0;
   end
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
     .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
     .UARTSin, .UARTSout, .SDCIntr);