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Removed P.FPGA from testbench.

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This commit is contained in:
Rose Thompson 2023-10-13 14:08:17 -05:00
parent c43377afff
commit c1d6fddea8
2 changed files with 17 additions and 21 deletions
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14
testbench/testbench-xcelium.sv
View File

@ -265,10 +265,8 @@ module testbench;
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find // declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// the addr of each label and fill the array. To expand, add more elements to this array // the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test) // and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!P.FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end end
end
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Verify the test ran correctly by checking the memory against a known signature. // Verify the test ran correctly by checking the memory against a known signature.
@ -361,21 +359,21 @@ module testbench;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// load memories with program image // load memories with program image
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED // this is a gross hack for xcelium and verilator
if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
always @(posedge clk) begin always @(posedge clk) begin
if (LoadMem) begin if (LoadMem) begin
if (P.FPGA) begin if (P.SDC_SUPPORTED) begin
`ifdef TB_FPGA `ifdef TB_SDC_SUPPORTED
string romfilename, sdcfilename; string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// shorten sdc timers for simulation // shorten sdc timers for simulation
dut.uncore.uncore.sdc.SDC.LimitTimers = 1; //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
`endif `endif
end end
else if (P.IROM_SUPPORTED) begin else if (P.IROM_SUPPORTED) begin

18
testbench/testbench.sv
View File

@ -37,9 +37,9 @@ module testbench;
parameter DEBUG=0; parameter DEBUG=0;
parameter TEST="none"; parameter TEST="none";
parameter PrintHPMCounters=1; parameter PrintHPMCounters=1;
parameter BPRED_LOGGER=0; parameter BPRED_LOGGER=1;
parameter I_CACHE_ADDR_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=1;
parameter D_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=1;
`include "parameter-defs.vh" `include "parameter-defs.vh"
@ -260,10 +260,8 @@ module testbench;
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find // declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// the addr of each label and fill the array. To expand, add more elements to this array // the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test) // and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!P.FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end end
end
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Verify the test ran correctly by checking the memory against a known signature. // Verify the test ran correctly by checking the memory against a known signature.
@ -344,14 +342,14 @@ module testbench;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin always @(posedge clk) begin
if (LoadMem) begin if (LoadMem) begin
if (P.FPGA) begin if (P.SDC_SUPPORTED) begin
string romfilename, sdcfilename; string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// shorten sdc timers for simulation // shorten sdc timers for simulation
dut.uncore.uncore.sdc.SDC.LimitTimers = 1; //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end end
else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
@ -377,7 +375,7 @@ module testbench;
assign {HRESPEXT, HRDATAEXT} = '0; assign {HRESPEXT, HRDATAEXT} = '0;
end end
if(P.FPGA) begin : sdcard if(P.SDC_SUPPORTED) begin : sdcard
// *** fix later // *** fix later
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
sdModel sdcard sdModel sdcard