Merge pull request #318 from harshinisrinath1001/main

Fixed the spacing of the cache module

src/cache/cache.sv

@@ -182,6 +182,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, W
       assign LineWriteData = FetchBuffer;
       assign LineByteMask = '1;
     end
+  
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
   /////////////////////////////////////////////////////////////////////////////////////////////

src/cache/cacheLRU.sv

@@ -104,8 +104,7 @@ module cacheLRU
     if (node == NUMWAYS-2) begin
       assign LRUUpdate[lchild] = ~WayEncoded[r];
       assign LRUUpdate[rchild] = WayEncoded[r];
-    end
-    else begin
+    end else begin
       assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
       assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
     end

src/cache/cacheway.sv

@@ -84,8 +84,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
     // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
     assign FlushWayEn = FlushWay & SelFlush;
     assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
-  end
-  else begin:flushlogic // no flush operation for read-only caches.
+  end else begin:flushlogic // no flush operation for read-only caches.
     assign SelTag = VictimWay;
     assign SelNonHit = SetValid;
   end
@@ -135,8 +134,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
-    end
-    else begin:wordram // no byte-enable needed for i$.
+    end else begin:wordram // no byte-enable needed for i$.
       ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
@@ -175,8 +173,4 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
       end
     end
   end else assign Dirty = 1'b0;
-
-
 endmodule
-
-

src/cache/subcachelineread.sv

@@ -43,9 +43,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
   logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0]   ReadDataLinePad;
   logic [WORDLEN-1:0]                         ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
 
-  if (PADLEN > 0) begin
-    assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
-  end else assign ReadDataLinePad = ReadDataLine;
+  if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
+  else            assign ReadDataLinePad = ReadDataLine;
 
   genvar index;
   for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux