From 19c1a0f99b5c4846de4931c10167432a695cc322 Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Fri, 9 Jun 2023 08:39:57 -0700 Subject: [PATCH 1/5] Update cache.sv Formatting clean up --- src/cache/cache.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 9dbc876fa..55e2ef03d 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -63,7 +63,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W localparam OFFSETLEN = $clog2(LINEBYTELEN); // Number of bits in offset field localparam SETLEN = $clog2(NUMLINES); // Number of set bits localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits - localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits + localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^ localparam FLUSHADRTHRESHOLD = NUMLINES - 1; // Used to determine when flush is complete @@ -182,6 +182,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W assign LineWriteData = FetchBuffer; assign LineByteMask = '1; end + ///////////////////////////////////////////////////////////////////////////////////////////// // Flush logic ///////////////////////////////////////////////////////////////////////////////////////////// From e7fb7403ef5aa0287e3ae8c2f3be64136287a853 Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Fri, 9 Jun 2023 08:43:38 -0700 Subject: [PATCH 2/5] Update cacheLRU.sv Code clean up --- src/cache/cacheLRU.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index e84c34dee..bf7d16834 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -104,8 +104,7 @@ module cacheLRU if (node == NUMWAYS-2) begin assign LRUUpdate[lchild] = ~WayEncoded[r]; assign LRUUpdate[rchild] = WayEncoded[r]; - end - else begin + end else begin assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r]; assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r]; end From c49232f0d27895569158ea554e5bd60e7ce9c956 Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Fri, 9 Jun 2023 08:48:11 -0700 Subject: [PATCH 3/5] Update cacheway.sv Code clean up --- src/cache/cacheway.sv | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 47c3de69c..81431c3b0 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -84,8 +84,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases. assign FlushWayEn = FlushWay & SelFlush; assign SelNonHit = FlushWayEn | SetValid | SelWriteback; - end - else begin:flushlogic // no flush operation for read-only caches. + end else begin:flushlogic // no flush operation for read-only caches. assign SelTag = VictimWay; assign SelNonHit = SetValid; end @@ -135,8 +134,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); - end - else begin:wordram // no byte-enable needed for i$. + end else begin:wordram // no byte-enable needed for i$. ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), @@ -154,8 +152,8 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = always_ff @(posedge clk) begin // Valid bit array, if (reset) ValidBits <= #1 '0; if(CacheEn) begin - ValidWay <= #1 ValidBits[CacheSet]; - if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway + ValidWay <= #1 ValidBits[CacheSet]; + if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay; end end @@ -175,8 +173,4 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = end end end else assign Dirty = 1'b0; - - endmodule - - From 570a628198d1b94ded77dac4b6421c5865b4567f Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Fri, 9 Jun 2023 08:50:51 -0700 Subject: [PATCH 4/5] Update subcachelineread.sv Code clean up --- src/cache/subcachelineread.sv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index ea305fb6c..a70a80b1e 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -43,9 +43,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN, logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad; logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; - if (PADLEN > 0) begin - assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine}; - end else assign ReadDataLinePad = ReadDataLine; + if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine}; + else assign ReadDataLinePad = ReadDataLine; genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux From aafa5d6ec3d4c5073f9077c7de9e65c82ba9c9dd Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Fri, 9 Jun 2023 08:53:27 -0700 Subject: [PATCH 5/5] Update ebu.sv Code clean up --- src/ebu/ebu.sv | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 5ceea8dc0..39975aa4b 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -37,25 +37,25 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( input logic [1:0] IFUHTRANS, // IFU AHB transaction request input logic [2:0] IFUHSIZE, // IFU AHB transaction size input logic [2:0] IFUHBURST, // IFU AHB burst length - input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address + input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant // Signals from LSU input logic [1:0] LSUHTRANS, // LSU AHB transaction request input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read input logic [2:0] LSUHSIZE, // LSU AHB size input logic [2:0] LSUHBURST, // LSU AHB burst length - input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address - input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN - input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask + input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address + input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready input logic HRESP, // AHB peripheral response. 0: OK 1: Error - output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic HWRITE, // AHB transaction direction after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration @@ -71,13 +71,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( logic IFUDisable; logic IFUSelect; - logic [PA_BITS-1:0] IFUHADDROut; + logic [PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [PA_BITS-1:0] LSUHADDROut; + logic [PA_BITS-1:0] LSUHADDROut; logic [1:0] LSUHTRANSOut; logic [2:0] LSUHBURSTOut; logic [2:0] LSUHSIZEOut;