Merge pull request #318 from harshinisrinath1001/main

Fixed the spacing of the cache module

src/cache/cache.sv

@@ -63,7 +63,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, W
   localparam                     OFFSETLEN = $clog2(LINEBYTELEN);    // Number of bits in offset field
   localparam                     SETLEN = $clog2(NUMLINES);          // Number of set bits
   localparam                     SETTOP = SETLEN+OFFSETLEN;          // Number of set plus offset bits
-  localparam                     TAGLEN = PA_BITS - SETTOP;         // Number of tag bits
+  localparam                     TAGLEN = PA_BITS - SETTOP;          // Number of tag bits
   localparam                     CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
   localparam                     LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
   localparam                     FLUSHADRTHRESHOLD = NUMLINES - 1;   // Used to determine when flush is complete
@@ -182,6 +182,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, W
       assign LineWriteData = FetchBuffer;
       assign LineByteMask = '1;
     end
+  
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
   /////////////////////////////////////////////////////////////////////////////////////////////

src/cache/cacheLRU.sv

@@ -104,8 +104,7 @@ module cacheLRU
     if (node == NUMWAYS-2) begin
       assign LRUUpdate[lchild] = ~WayEncoded[r];
       assign LRUUpdate[rchild] = WayEncoded[r];
-    end
+    end else begin
-    else begin
       assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
       assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
     end

src/cache/cacheway.sv

@@ -84,8 +84,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
     // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
     assign FlushWayEn = FlushWay & SelFlush;
     assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
-  end
+  end else begin:flushlogic // no flush operation for read-only caches.
-  else begin:flushlogic // no flush operation for read-only caches.
     assign SelTag = VictimWay;
     assign SelNonHit = SetValid;
   end
@@ -135,8 +134,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
-    end
+    end else begin:wordram // no byte-enable needed for i$.
-    else begin:wordram // no byte-enable needed for i$.
       ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
@@ -154,8 +152,8 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
   always_ff @(posedge clk) begin // Valid bit array, 
     if (reset) ValidBits        <= #1 '0;
     if(CacheEn) begin 
-    ValidWay <= #1 ValidBits[CacheSet];
+      ValidWay <= #1 ValidBits[CacheSet];
-    if(InvalidateCache)                    ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
+      if(InvalidateCache)                    ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
       else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay;
     end
   end
@@ -175,8 +173,4 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
       end
     end
   end else assign Dirty = 1'b0;
-
-
 endmodule
-
-

src/cache/subcachelineread.sv

@@ -43,9 +43,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
   logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0]   ReadDataLinePad;
   logic [WORDLEN-1:0]                         ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
 
-  if (PADLEN > 0) begin
+  if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
-    assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
+  else            assign ReadDataLinePad = ReadDataLine;
-  end else assign ReadDataLinePad = ReadDataLine;
 
   genvar index;
   for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux

src/ebu/ebu.sv

@@ -37,25 +37,25 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
   input  logic [1:0]          IFUHTRANS, // IFU AHB transaction request
   input  logic [2:0]          IFUHSIZE,  // IFU AHB transaction size
   input  logic [2:0]          IFUHBURST, // IFU AHB burst length
-  input  logic [PA_BITS-1:0] IFUHADDR,  // IFU AHB address
+  input  logic [PA_BITS-1:0]  IFUHADDR,  // IFU AHB address
   output logic                IFUHREADY, // AHB peripheral ready gated by possible non-grant
   // Signals from LSU
   input  logic [1:0]          LSUHTRANS, // LSU AHB transaction request
   input  logic                LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
   input  logic [2:0]          LSUHSIZE,  // LSU AHB size
   input  logic [2:0]          LSUHBURST, // LSU AHB burst length
-  input  logic [PA_BITS-1:0] LSUHADDR,  // LSU AHB address
+  input  logic [PA_BITS-1:0]  LSUHADDR,  // LSU AHB address
-  input  logic [XLEN-1:0]    LSUHWDATA, // initially support AHBW = XLEN
+  input  logic [XLEN-1:0]     LSUHWDATA, // initially support AHBW = XLEN
-  input  logic [XLEN/8-1:0]  LSUHWSTRB, // AHB byte mask
+  input  logic [XLEN/8-1:0]   LSUHWSTRB, // AHB byte mask
   output logic                LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
 
   // AHB-Lite external signals
   output logic                HCLK, HRESETn, 
   input  logic                HREADY,    // AHB peripheral ready
   input  logic                HRESP,     // AHB peripheral response. 0: OK 1: Error
-  output logic [PA_BITS-1:0] HADDR,     // AHB address to peripheral after arbitration
+  output logic [PA_BITS-1:0]  HADDR,     // AHB address to peripheral after arbitration
-  output logic [AHBW-1:0]    HWDATA,    // AHB Write data after arbitration
+  output logic [AHBW-1:0]     HWDATA,    // AHB Write data after arbitration
-  output logic [XLEN/8-1:0]  HWSTRB,    // AHB byte write enables after arbitration
+  output logic [XLEN/8-1:0]   HWSTRB,    // AHB byte write enables after arbitration
   output logic                HWRITE,    // AHB transaction direction after arbitration
   output logic [2:0]          HSIZE,     // AHB transaction size after arbitration
   output logic [2:0]          HBURST,    // AHB burst length after arbitration
@@ -71,13 +71,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
   logic                       IFUDisable;
   logic                       IFUSelect;
 
-  logic [PA_BITS-1:0]        IFUHADDROut;
+  logic [PA_BITS-1:0]         IFUHADDROut;
   logic [1:0]                 IFUHTRANSOut;
   logic [2:0]                 IFUHBURSTOut;
   logic [2:0]                 IFUHSIZEOut;
   logic                       IFUHWRITEOut;
   
-  logic [PA_BITS-1:0]        LSUHADDROut;
+  logic [PA_BITS-1:0]         LSUHADDROut;
   logic [1:0]                 LSUHTRANSOut;
   logic [2:0]                 LSUHBURSTOut;
   logic [2:0]                 LSUHSIZEOut;