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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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@ -63,7 +63,7 @@ module hazard(
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assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
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assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
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assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
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assign StallMCause = wfiM & ~TrapM; // 0; // *** dh for wfi
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assign StallMCause = wfiM & ~TrapM;
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assign StallWCause = LSUStallM | IFUStallF;
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assign StallWCause = LSUStallM | IFUStallF;
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assign StallF = StallFCause | StallD;
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assign StallF = StallFCause | StallD;
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@ -41,7 +41,7 @@ module csr #(parameter
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input logic StallE, StallM, StallW,
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input logic StallE, StallM, StallW,
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input logic [31:0] InstrM,
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input logic [31:0] InstrM,
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input logic [`XLEN-1:0] PCM, SrcAM,
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input logic [`XLEN-1:0] PCM, SrcAM,
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input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM,
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input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM,
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input logic TimerIntM, MExtIntM, SExtIntM, SwIntM,
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input logic TimerIntM, MExtIntM, SExtIntM, SwIntM,
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input logic [63:0] MTIME_CLINT,
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input logic [63:0] MTIME_CLINT,
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input logic InstrValidM, FRegWriteM, LoadStallD,
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input logic InstrValidM, FRegWriteM, LoadStallD,
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@ -124,7 +124,7 @@ module csr #(parameter
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// write CSRs
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// write CSRs
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assign CSRAdrM = InstrM[31:20];
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assign CSRAdrM = InstrM[31:20];
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assign UnalignedNextEPCM = TrapM ? (wfiM ? PCM+4 : PCM) : CSRWriteValM;
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assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM;
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assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
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assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
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assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
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assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
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assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
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assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
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@ -135,7 +135,7 @@ module privileged (
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///////////////////////////////////////////
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///////////////////////////////////////////
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// WFI timeout Privileged Spec 3.1.6.5
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// WFI timeout Privileged Spec 3.1.6.5
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///////////////////////////////////////////
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///////////////////////////////////////////
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if (`U_SUPPORTED) begin
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if (`U_SUPPORTED) begin:wfi
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logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
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logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
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assign WFICountPlus1 = WFICount + 1;
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assign WFICountPlus1 = WFICount + 1;
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floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI
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floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI
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@ -158,7 +158,7 @@ module privileged (
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.FlushE, .FlushM, .FlushW,
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.FlushE, .FlushM, .FlushW,
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.StallE, .StallM, .StallW,
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.StallE, .StallM, .StallW,
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.InstrM, .PCM, .SrcAM,
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.InstrM, .PCM, .SrcAM,
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.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM,
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.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM,
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.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM,
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.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM,
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.MTIME_CLINT,
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.MTIME_CLINT,
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.InstrValidM, .FRegWriteM, .LoadStallD,
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.InstrValidM, .FRegWriteM, .LoadStallD,
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@ -1550,7 +1550,7 @@ string wally32i[] = '{
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"rv32i_m/privilege/WALLY-status-mie-01", "5080",
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"rv32i_m/privilege/WALLY-status-mie-01", "5080",
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"rv32i_m/privilege/WALLY-status-sie-01", "5080",
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"rv32i_m/privilege/WALLY-status-sie-01", "5080",
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"rv32i_m/privilege/WALLY-trap-sret-01", "5080",
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"rv32i_m/privilege/WALLY-trap-sret-01", "5080",
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// "rv32i_m/privilege/WALLY-status-tw-01", "5080", *** this test doesn't pass yet because PC counts up while wfi is spinning
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"rv32i_m/privilege/WALLY-status-tw-01", "5080",
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"rv32i_m/privilege/WALLY-wfi-01", "5080"
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"rv32i_m/privilege/WALLY-wfi-01", "5080"
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};
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};
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@ -2,7 +2,7 @@
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00000000 # mtval of ecall (*** defined to be zero for now)
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00000000 # mtval of ecall (*** defined to be zero for now)
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00001800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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00001800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000002 # mcause from an Illegal instruction
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00000002 # mcause from an Illegal instruction
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00000000 # mtval of faulting instruction (0x0)
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10500073 # mtval of faulting instruction (wfi)
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00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000009 # mcause from S mode ecall from test termination
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00000009 # mcause from S mode ecall from test termination
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00000000 # mtval of ecall (*** defined to be zero for now)
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00000000 # mtval of ecall (*** defined to be zero for now)
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@ -6,7 +6,7 @@
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00000000
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00000000
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00000002 # mcause from an Illegal instruction
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00000002 # mcause from an Illegal instruction
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00000000
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00000000
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00000000 # mtval of faulting instruction (0x0)
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10500073 # mtval of faulting instruction (wfi)
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00000000
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00000000
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00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000000
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00000000
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