From c100c9893b378c6d452c2b43725203ed061ec257 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 5 May 2022 14:37:21 +0000 Subject: [PATCH] wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts --- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/privileged/csr.sv | 4 ++-- pipelined/src/privileged/privileged.sv | 4 ++-- pipelined/testbench/tests.vh | 2 +- .../privilege/references/WALLY-status-tw-01.reference_output | 2 +- .../privilege/references/WALLY-status-tw-01.reference_output | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 70e8e5f51..bb45003f8 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -63,7 +63,7 @@ module hazard( assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE); assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); - assign StallMCause = wfiM & ~TrapM; // 0; // *** dh for wfi + assign StallMCause = wfiM & ~TrapM; assign StallWCause = LSUStallM | IFUStallF; assign StallF = StallFCause | StallD; diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index f35050b78..006ef4cc4 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -41,7 +41,7 @@ module csr #(parameter input logic StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, - input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, + input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM, input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, @@ -124,7 +124,7 @@ module csr #(parameter // write CSRs assign CSRAdrM = InstrM[31:20]; - assign UnalignedNextEPCM = TrapM ? (wfiM ? PCM+4 : PCM) : CSRWriteValM; + assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? CauseM : CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 4e794806a..96ec84014 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -135,7 +135,7 @@ module privileged ( /////////////////////////////////////////// // WFI timeout Privileged Spec 3.1.6.5 /////////////////////////////////////////// - if (`U_SUPPORTED) begin + if (`U_SUPPORTED) begin:wfi logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; assign WFICountPlus1 = WFICount + 1; floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI @@ -158,7 +158,7 @@ module privileged ( .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, - .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, + .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM, .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index ebf91c86c..46295ce17 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1550,7 +1550,7 @@ string wally32i[] = '{ "rv32i_m/privilege/WALLY-status-mie-01", "5080", "rv32i_m/privilege/WALLY-status-sie-01", "5080", "rv32i_m/privilege/WALLY-trap-sret-01", "5080", -// "rv32i_m/privilege/WALLY-status-tw-01", "5080", *** this test doesn't pass yet because PC counts up while wfi is spinning + "rv32i_m/privilege/WALLY-status-tw-01", "5080", "rv32i_m/privilege/WALLY-wfi-01", "5080" }; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output index 9b12e4f56..f37485d3a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output @@ -2,7 +2,7 @@ 00000000 # mtval of ecall (*** defined to be zero for now) 00001800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 00000002 # mcause from an Illegal instruction -00000000 # mtval of faulting instruction (0x0) +10500073 # mtval of faulting instruction (wfi) 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 00000009 # mcause from S mode ecall from test termination 00000000 # mtval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output index aa723ea7d..5e277ede9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output @@ -6,7 +6,7 @@ 00000000 00000002 # mcause from an Illegal instruction 00000000 -00000000 # mtval of faulting instruction (0x0) +10500073 # mtval of faulting instruction (wfi) 00000000 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000