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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Tied dangling signals to 0 for some configs to make VCS lint happy
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@ -286,17 +286,19 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign IFUHBURST = 3'b0;
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assign IFUHBURST = 3'b0;
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assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
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assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
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end
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end
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// mux between the alignments of uncached reads.
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if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16],
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FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
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PCSpillF[2:1], ShiftUncachedInstr);
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else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
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end else begin : nobus // block: bus
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end else begin : nobus // block: bus
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assign {BusStall, CacheCommittedF} = '0;
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assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS,
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BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;
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assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
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assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
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assign InstrRawF = IROMInstrF;
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assign InstrRawF = IROMInstrF;
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end
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end
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// mux between the alignments of uncached reads.
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if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
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PCSpillF[2:1], ShiftUncachedInstr);
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else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
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assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
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assign GatedStallD = StallD & ~SelSpillNextF;
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assign GatedStallD = StallD & ~SelSpillNextF;
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@ -383,7 +383,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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end
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end else begin: nobus // block: bus, only DTIM
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end else begin: nobus // block: bus, only DTIM
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assign LSUHWDATA = '0;
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assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0;
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assign DCacheReadDataWordM = '0;
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assign ReadDataWordMuxM = DTIMReadDataWordM;
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assign ReadDataWordMuxM = DTIMReadDataWordM;
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assign {BusStall, BusCommittedM} = '0;
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assign {BusStall, BusCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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@ -52,6 +52,7 @@ module subwordread import cvw::*; #(parameter cvw_t P) (
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// Use indexed part select to imply muxes to select each size of subword
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// Use indexed part select to imply muxes to select each size of subword
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if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM);
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if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM);
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else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM;
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else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM;
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else assign DblWordM = '0; // unused for RV32F
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if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM);
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if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM);
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else assign WordM = ReadDataWordMuxM;
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else assign WordM = ReadDataWordMuxM;
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mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM);
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mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM);
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@ -264,6 +264,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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.HPROT, .HTRANS, .HMASTLOCK);
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end else begin
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assign {IFUHREADY, LSUHREADY, HCLK, HRESETn, HADDR, HWDATA,
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HWSTRB, HWRITE, HSIZE, HBURST, HPROT, HTRANS, HMASTLOCK} = '0;
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end
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end
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// global stall and flush control
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// global stall and flush control
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@ -302,15 +305,12 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
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end else begin
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end else begin
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assign CSRReadValW = '0;
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assign {CSRReadValW, PrivilegeModeW,
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assign EPCM = '0;
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SATP_REGW, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_MPP, STATUS_FS, FRM_REGW,
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assign TrapVectorM = '0;
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// PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW,
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assign RetM = 1'b0;
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ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE,
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assign TrapM = 1'b0;
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EPCM, TrapVectorM, RetM, TrapM,
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assign wfiM = 1'b0;
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sfencevmaM, BigEndianM, wfiM, IntPendingM} = '0;
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assign IntPendingM = 1'b0;
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assign sfencevmaM = 1'b0;
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assign BigEndianM = 1'b0;
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end
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end
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// multiply/divide unit
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// multiply/divide unit
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@ -351,15 +351,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.SetFflagsM, // FPU flags (to privileged unit)
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.SetFflagsM, // FPU flags (to privileged unit)
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.FIntDivResultW);
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.FIntDivResultW);
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end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
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end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
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assign FPUStallD = 1'b0;
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assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW,
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assign FWriteIntE = 1'b0;
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IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
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assign FCvtIntE = 1'b0;
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FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0;
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assign FIntResM = '0;
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assign FCvtIntW = 1'b0;
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assign FDivBusyE = 1'b0;
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assign IllegalFPUInstrD = 1'b1;
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assign SetFflagsM = '0;
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assign FpLoadStoreM = 1'b0;
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end
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end
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endmodule
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endmodule
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@ -85,6 +85,9 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
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.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
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.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
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.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin,
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.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin,
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.UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
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.UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
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end else begin
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assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt,
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MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0;
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end
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end
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endmodule
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endmodule
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