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Steps to getting branch predictor benchmarks running.

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This commit is contained in:
Ross Thompson 2021-04-06 21:20:51 -05:00
parent 9172e52286
commit bff2d61a1f
8 changed files with 183 additions and 93 deletions
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2
testsBP/crt0/start.s
View File

@ -45,7 +45,7 @@ _start:
# set the stack pointer to the top of memory # set the stack pointer to the top of memory
# 0x8000_0000 + 64K - 8 bytes # 0x8000_0000 + 64K - 8 bytes
li sp, 0x0000FFF8 li sp, 0x007FFFF8
jal ra, main jal ra, main
jal ra, _halt jal ra, _halt

1
testsBP/makefile.inc
View File

@ -90,3 +90,4 @@ $(TARGET).memfile: $(TARGET)
@echo 'Making memory file' @echo 'Making memory file'
exe2memfile0.pl $< exe2memfile0.pl $<
extractFunctionRadix.sh $<.objdump extractFunctionRadix.sh $<.objdump
cp $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/

1
testsBP/simple/header.h
View File

@ -3,4 +3,5 @@
int fail(); int fail();
int simple_csrbr_test(); int simple_csrbr_test();
int lbu_test();
#endif #endif

1
testsBP/simple/main.c
View File

@ -6,5 +6,6 @@ int main(){
fail(); fail();
return 0; return 0;
}else }else
res = lbu_test();
return 0; return 0;
} }

120
wally-pipelined/bin/exe2memfile0.pl
View File

@ -18,7 +18,7 @@ my $maxaddress = 0;
STDOUT->autoflush(1); STDOUT->autoflush(1);
# *** Ross Thompson I think there is a bug here needs to be +1 # *** Ross Thompson I think there is a bug here needs to be +1
print ("Processing $#ARGV memfiles: "); print ("Processing $#ARGV memfiles: \n");
my $frac = $#ARGV/10; my $frac = $#ARGV/10;
for(my $i=0; $i<=$#ARGV; $i++) { for(my $i=0; $i<=$#ARGV; $i++) {
if ($i < 10 || $i % $frac == 0) { print ("$i ") }; if ($i < 10 || $i % $frac == 0) { print ("$i ") };
@ -40,7 +40,11 @@ for(my $i=0; $i<=$#ARGV; $i++) {
if ($needsprocessing == 1) { if ($needsprocessing == 1) {
open(FILE, $ofile) || die("Can't read $ofile"); open(FILE, $ofile) || die("Can't read $ofile");
my $mode = 0; # parse for code my $mode = 0; # parse for code
my $section = "";
my $data = "";
my $address; my $address;
my $first = 0;
my $firstAddress;
# initialize to all zeros; # initialize to all zeros;
# *** need to fix the zeroing range. Not always 64K # *** need to fix the zeroing range. Not always 64K
@ -49,57 +53,100 @@ for(my $i=0; $i<=$#ARGV; $i++) {
} }
while(<FILE>) { while(<FILE>) {
# *** this mode stuff does not work if a section is missing or reordered. # objdump fill is divided into several .sections of which only some we want to actually process.
if ($mode == 0) { # Parse code # In general we want everything except the .comment and .*attributes
# print("Examining $_\n"); if (/Disassembly of section (.*):/) {
if (/^\s*(\S{1,16}):\s+(\S+)\s+/) { $section = $1;
$address = &fixadr($1); print ("setting section to $section\n");
my $instr = $2; } else {
my $len = length($instr); # now check if the section is one we are interested in processing.
for (my $i=0; $i<$len/2; $i++) { #if ($section ne ".comment" && $section ne ".riscv.attributes" && $section =~ /\.debug.*/) {
$memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2); if ($section =~ "\.init|\.text|\..*data|\..*bss") {
} # the structure is: possible space(s) hex number: possible space(s) hex number space(s) junk
# print ("address $address $instr\n"); # there are also lines we need to skip: possible space(s) hex number <string>:
if (/^\s*([0-9A-Fa-f]{1,16}):\s+([0-9A-Fa-f]+).*$/) {
$address = &fixadr($1);
if ($first == 0) {
$first = 1;
$firstAddress = $address;
}
$data = $2;
&emitData($address, $data);
# my $len = length($data);
# for (my $i=0; $i<$len/2; $i++) {
# $memfilebytes[$address+$i] = substr($data, $len-2-2*$i, 2);
# }
# print ("Addr $address $data\n");
# } elsif (/^\s*\.\.\./) {
# print ("Got ...\n");
# } else {
# print ("No match\n");
}
} }
if (/Disassembly of section .data:/) { $mode = 1;} }
} elsif ($mode == 1) { # Parse data segment # # *** this mode stuff does not work if a section is missing or reordered.
if (/^\s*(\S{1,16}):\s+(.*)/) { # if ($mode == 0) { # Parse code
$address = &fixadr($1); # # print("Examining $_\n");
# print "addresss $address maxaddress $maxaddress\n"; # if (/^\s*(\S{1,16}):\s+(\S+)\s+/) {
if ($address > $maxaddress) { $maxaddress = $address; } # $address = &fixadr($1);
my $line = $2; # my $instr = $2;
# merge chunks with spaces # my $len = length($instr);
# *** might need to change # for (my $i=0; $i<$len/2; $i++) {
$line =~ s/(\S)\s(\S)/$1$2/g; # $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2);
# strip off comments # }
$line =~ /^(\S*)/; # print ("address $address $instr\n");
$payload = $1; # }
&emitData($address, $payload); # if (/Disassembly of section .data:/) { $mode = 1;}
} # } elsif ($mode == 1) { # Parse data segment
if (/Disassembly of section .comment:/) { $mode = 2; } # if (/^\s*(\S{1,16}):\s+(.*)/) {
} elsif ($mode == 2) { # parse the comment section # $address = &fixadr($1);
if (/Disassembly of section .riscv.attributes:/) { $mode = 3; } # # print "addresss $address maxaddress $maxaddress\n";
} # if ($address > $maxaddress) { $maxaddress = $address; }
# my $line = $2;
# # merge chunks with spaces
# # *** might need to change
# $line =~ s/(\S)\s(\S)/$1$2/g;
# # strip off comments
# $line =~ /^(\S*)/;
# $payload = $1;
# &emitData($address, $payload);
# }
# if (/Disassembly of section .comment:/) { $mode = 2; }
# } elsif ($mode == 2) { # parse the comment section
# if (/Disassembly of section .riscv.attributes:/) { $mode = 3; }
# }
} }
close(FILE); close(FILE);
$maxaddress += 32; # pad some zeros at the end $maxaddress = $address + 32; # pad some zeros at the end
# print to memory file # print to memory file
# *** this is a problem # *** this is a problem
if ($fname =~ /rv32/) { if ($fname =~ /rv32/) {
open(MEMFILE, ">$memfile") || die("Can't write $memfile"); open(MEMFILE, ">$memfile") || die("Can't write $memfile");
for (my $i=0; $i<= $maxaddress; $i = $i + 4) { for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 4) {
for ($j=3; $j>=0; $j--) { for ($j=3; $j>=0; $j--) {
print MEMFILE "$memfilebytes[$i+$j]"; no warnings 'uninitialized';
my $value = $memfilebytes[$i+$j];
if ($value eq ""){
print MEMFILE "00";
} else {
print MEMFILE "$memfilebytes[$i+$j]";
}
} }
print MEMFILE "\n"; print MEMFILE "\n";
} }
close(MEMFILE); close(MEMFILE);
} else { } else {
open(MEMFILE, ">$memfile") || die("Can't write $memfile"); open(MEMFILE, ">$memfile") || die("Can't write $memfile");
for (my $i=0; $i<= $maxaddress; $i = $i + 8) { for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 8) {
for ($j=7; $j>=0; $j--) { for ($j=7; $j>=0; $j--) {
print MEMFILE "$memfilebytes[$i+$j]"; no warnings 'uninitialized';
my $value = $memfilebytes[$i+$j];
if ($value eq ""){
print MEMFILE "00";
} else {
print MEMFILE "$memfilebytes[$i+$j]";
}
} }
print MEMFILE "\n"; print MEMFILE "\n";
} }
@ -141,5 +188,6 @@ sub fixadr {
# strip off leading 8 from address and convert to decimal # strip off leading 8 from address and convert to decimal
# if the leading 8 is not present don't remove. # if the leading 8 is not present don't remove.
my $adr = shift; my $adr = shift;
#print "addr $adr\n";
return hex($adr); return hex($adr);
} }

20
wally-pipelined/config/rv64BP/wally-config.vh
View File

@ -66,18 +66,18 @@
// Peripheral memory space extends from BASE to BASE+RANGE // Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define BOOTTIMBASE 32'h00080000 `define BOOTTIMBASE 32'h00800000
`define BOOTTIMRANGE 32'h00003FFF `define BOOTTIMRANGE 32'h00003FFF
`define TIMBASE 32'h00000000 `define TIMBASE 32'h00000000
`define TIMRANGE 32'h0007FFFF `define TIMRANGE 32'h007FFFFF
`define CLINTBASE 32'h02000000 `define CLINTBASE 32'h02000000
`define CLINTRANGE 32'h0000FFFF `define CLINTRANGE 32'h0000FFFF
`define GPIOBASE 32'h10012000 `define GPIOBASE 32'h10012000
`define GPIORANGE 32'h000000FF `define GPIORANGE 32'h000000FF
`define UARTBASE 32'h10000000 `define UARTBASE 32'h10000000
`define UARTRANGE 32'h00000007 `define UARTRANGE 32'h00000007
`define PLICBASE 32'h0C000000 `define PLICBASE 32'h0C000000
`define PLICRANGE 32'h03FFFFFF `define PLICRANGE 32'h03FFFFFF
// Test modes // Test modes

130
wally-pipelined/regression/wave.do
View File

@ -56,15 +56,14 @@ add wave -noupdate -group Bpred -expand -group direction -group other /testbench
add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/DoForwardingF add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/DoForwardingF
add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRD add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRD
add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRE add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE add wave -noupdate -group Bpred -expand -group {bp wrong} -divider pcs
add wave -noupdate -group Bpred -group {bp wrong} -divider pcs add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE
add wave -noupdate -group Bpred -expand -group BTB -divider Update add wave -noupdate -group Bpred -expand -group BTB -divider Update
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
@ -96,25 +95,25 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
@ -128,10 +127,11 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate /testbench/InstrFName add wave -noupdate /testbench/InstrFName
add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM
add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM add wave -noupdate -expand -group dcache -radix hexadecimal /testbench/dut/hart/MemPAdrM
add wave -noupdate -group dcache /testbench/dut/hart/WriteDataM add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM
add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemRWM add wave -noupdate -expand -group dcache /testbench/dut/hart/ReadDataW
add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@ -150,15 +150,15 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALURe
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group PCS /testbench/dut/hart/PCF add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -group PCS /testbench/dut/hart/PCE add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
add wave -noupdate -group PCS /testbench/dut/hart/PCM add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCW add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW
add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNextF add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext0F add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext1F add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr
add wave -noupdate -group {function radix debug} -radix unsigned /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate -group {function radix debug} -radix unsigned /testbench/FunctionName/FunctionName/ProgramAddrIndex
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/reset add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/reset
@ -173,15 +173,53 @@ add wave -noupdate -group {function radix debug} /testbench/FunctionName/Functio
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/ProgramAddrIndex
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultW add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultW
add wave -noupdate /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/CSRCReadValM add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/CSRCReadValM
add wave -noupdate -radix unsigned /testbench/dut/imem/adrbits
add wave -noupdate /testbench/dut/imem/rd
add wave -noupdate /testbench/dut/imem/AdrF
add wave -noupdate /testbench/dut/imem/InstrF
add wave -noupdate /testbench/dut/InstrF
add wave -noupdate /testbench/dut/InstrF
add wave -noupdate -divider {New Divider}
add wave -noupdate /testbench/dut/hart/ifu/InstrInF
add wave -noupdate /testbench/dut/hart/ifu/rd2
add wave -noupdate /testbench/dut/hart/InstrRData
add wave -noupdate /testbench/dut/hart/rd2
add wave -noupdate /testbench/dut/hart/ebu/InstrRData
add wave -noupdate /testbench/dut/hart/ebu/InstrPAdrF
add wave -noupdate /testbench/dut/hart/ebu/HRDATA
add wave -noupdate /testbench/dut/uncore/HSELUARTD
add wave -noupdate /testbench/dut/uncore/HSELUART
add wave -noupdate /testbench/dut/uncore/HSELTimD
add wave -noupdate /testbench/dut/uncore/HSELTim
add wave -noupdate /testbench/dut/uncore/HSELPLICD
add wave -noupdate /testbench/dut/uncore/HSELPLIC
add wave -noupdate /testbench/dut/uncore/HSELGPIOD
add wave -noupdate /testbench/dut/uncore/HSELGPIO
add wave -noupdate /testbench/dut/uncore/HSELCLINTD
add wave -noupdate /testbench/dut/uncore/HSELCLINT
add wave -noupdate /testbench/dut/uncore/HSELBootTimD
add wave -noupdate /testbench/dut/uncore/HSELBootTim
add wave -noupdate /testbench/dut/uncore/HREADTim
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0
add wave -noupdate /testbench/dut/uncore/dtim/BASE
add wave -noupdate /testbench/dut/uncore/dtim/RANGE
add wave -noupdate /testbench/memfilename
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[770056]}
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[771306]}
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR
add wave -noupdate /testbench/dut/uncore/dtim/RAM
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 7} {13518 ns} 0} WaveRestoreCursors {{Cursor 7} {15047768 ns} 0} {{Cursor 2} {34763538 ns} 0} {{Cursor 3} {15046271 ns} 0} {{Cursor 4} {15047307 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 229 configure wave -valuecolwidth 229
@ -197,4 +235,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {13489 ns} {13607 ns} WaveRestoreZoom {15047734 ns} {15047902 ns}

1
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -317,6 +317,7 @@ string tests32i[] = {
string testsBP64[] = '{ string testsBP64[] = '{
"rv64BP/simple", "10000", "rv64BP/simple", "10000",
"rv64BP/qsort", "1000000",
"rv64BP/sieve", "1000000" "rv64BP/sieve", "1000000"
}; };
string tests[]; string tests[];