diff --git a/testsBP/crt0/start.s b/testsBP/crt0/start.s index 175435817..19a240d87 100644 --- a/testsBP/crt0/start.s +++ b/testsBP/crt0/start.s @@ -45,7 +45,7 @@ _start: # set the stack pointer to the top of memory # 0x8000_0000 + 64K - 8 bytes - li sp, 0x0000FFF8 + li sp, 0x007FFFF8 jal ra, main jal ra, _halt diff --git a/testsBP/makefile.inc b/testsBP/makefile.inc index af0b03bc5..141b5d91e 100644 --- a/testsBP/makefile.inc +++ b/testsBP/makefile.inc @@ -90,3 +90,4 @@ $(TARGET).memfile: $(TARGET) @echo 'Making memory file' exe2memfile0.pl $< extractFunctionRadix.sh $<.objdump + cp $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ diff --git a/testsBP/simple/header.h b/testsBP/simple/header.h index b5268fbfa..a52bf804b 100644 --- a/testsBP/simple/header.h +++ b/testsBP/simple/header.h @@ -3,4 +3,5 @@ int fail(); int simple_csrbr_test(); +int lbu_test(); #endif diff --git a/testsBP/simple/main.c b/testsBP/simple/main.c index 047a52f84..97adcb7ca 100644 --- a/testsBP/simple/main.c +++ b/testsBP/simple/main.c @@ -6,5 +6,6 @@ int main(){ fail(); return 0; }else + res = lbu_test(); return 0; } diff --git a/wally-pipelined/bin/exe2memfile0.pl b/wally-pipelined/bin/exe2memfile0.pl index 8fbea6f8d..1b0dad536 100755 --- a/wally-pipelined/bin/exe2memfile0.pl +++ b/wally-pipelined/bin/exe2memfile0.pl @@ -18,7 +18,7 @@ my $maxaddress = 0; STDOUT->autoflush(1); # *** Ross Thompson I think there is a bug here needs to be +1 -print ("Processing $#ARGV memfiles: "); +print ("Processing $#ARGV memfiles: \n"); my $frac = $#ARGV/10; for(my $i=0; $i<=$#ARGV; $i++) { if ($i < 10 || $i % $frac == 0) { print ("$i ") }; @@ -40,7 +40,11 @@ for(my $i=0; $i<=$#ARGV; $i++) { if ($needsprocessing == 1) { open(FILE, $ofile) || die("Can't read $ofile"); my $mode = 0; # parse for code + my $section = ""; + my $data = ""; my $address; + my $first = 0; + my $firstAddress; # initialize to all zeros; # *** need to fix the zeroing range. Not always 64K @@ -49,57 +53,100 @@ for(my $i=0; $i<=$#ARGV; $i++) { } while() { - # *** this mode stuff does not work if a section is missing or reordered. - if ($mode == 0) { # Parse code -# print("Examining $_\n"); - if (/^\s*(\S{1,16}):\s+(\S+)\s+/) { - $address = &fixadr($1); - my $instr = $2; - my $len = length($instr); - for (my $i=0; $i<$len/2; $i++) { - $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2); - } -# print ("address $address $instr\n"); + # objdump fill is divided into several .sections of which only some we want to actually process. + # In general we want everything except the .comment and .*attributes + if (/Disassembly of section (.*):/) { + $section = $1; + print ("setting section to $section\n"); + } else { + # now check if the section is one we are interested in processing. + #if ($section ne ".comment" && $section ne ".riscv.attributes" && $section =~ /\.debug.*/) { + if ($section =~ "\.init|\.text|\..*data|\..*bss") { + # the structure is: possible space(s) hex number: possible space(s) hex number space(s) junk + # there are also lines we need to skip: possible space(s) hex number : + if (/^\s*([0-9A-Fa-f]{1,16}):\s+([0-9A-Fa-f]+).*$/) { + $address = &fixadr($1); + if ($first == 0) { + $first = 1; + $firstAddress = $address; + } + $data = $2; + &emitData($address, $data); + # my $len = length($data); + # for (my $i=0; $i<$len/2; $i++) { + # $memfilebytes[$address+$i] = substr($data, $len-2-2*$i, 2); + # } +# print ("Addr $address $data\n"); +# } elsif (/^\s*\.\.\./) { +# print ("Got ...\n"); +# } else { +# print ("No match\n"); + } } - if (/Disassembly of section .data:/) { $mode = 1;} - } elsif ($mode == 1) { # Parse data segment - if (/^\s*(\S{1,16}):\s+(.*)/) { - $address = &fixadr($1); -# print "addresss $address maxaddress $maxaddress\n"; - if ($address > $maxaddress) { $maxaddress = $address; } - my $line = $2; - # merge chunks with spaces - # *** might need to change - $line =~ s/(\S)\s(\S)/$1$2/g; - # strip off comments - $line =~ /^(\S*)/; - $payload = $1; - &emitData($address, $payload); - } - if (/Disassembly of section .comment:/) { $mode = 2; } - } elsif ($mode == 2) { # parse the comment section - if (/Disassembly of section .riscv.attributes:/) { $mode = 3; } - } + } +# # *** this mode stuff does not work if a section is missing or reordered. +# if ($mode == 0) { # Parse code +# # print("Examining $_\n"); +# if (/^\s*(\S{1,16}):\s+(\S+)\s+/) { +# $address = &fixadr($1); +# my $instr = $2; +# my $len = length($instr); +# for (my $i=0; $i<$len/2; $i++) { +# $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2); +# } +# print ("address $address $instr\n"); +# } +# if (/Disassembly of section .data:/) { $mode = 1;} +# } elsif ($mode == 1) { # Parse data segment +# if (/^\s*(\S{1,16}):\s+(.*)/) { +# $address = &fixadr($1); +# # print "addresss $address maxaddress $maxaddress\n"; +# if ($address > $maxaddress) { $maxaddress = $address; } +# my $line = $2; +# # merge chunks with spaces +# # *** might need to change +# $line =~ s/(\S)\s(\S)/$1$2/g; +# # strip off comments +# $line =~ /^(\S*)/; +# $payload = $1; +# &emitData($address, $payload); +# } +# if (/Disassembly of section .comment:/) { $mode = 2; } +# } elsif ($mode == 2) { # parse the comment section +# if (/Disassembly of section .riscv.attributes:/) { $mode = 3; } +# } } close(FILE); - $maxaddress += 32; # pad some zeros at the end + $maxaddress = $address + 32; # pad some zeros at the end # print to memory file # *** this is a problem if ($fname =~ /rv32/) { open(MEMFILE, ">$memfile") || die("Can't write $memfile"); - for (my $i=0; $i<= $maxaddress; $i = $i + 4) { + for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 4) { for ($j=3; $j>=0; $j--) { - print MEMFILE "$memfilebytes[$i+$j]"; + no warnings 'uninitialized'; + my $value = $memfilebytes[$i+$j]; + if ($value eq ""){ + print MEMFILE "00"; + } else { + print MEMFILE "$memfilebytes[$i+$j]"; + } } print MEMFILE "\n"; } close(MEMFILE); } else { open(MEMFILE, ">$memfile") || die("Can't write $memfile"); - for (my $i=0; $i<= $maxaddress; $i = $i + 8) { + for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 8) { for ($j=7; $j>=0; $j--) { - print MEMFILE "$memfilebytes[$i+$j]"; + no warnings 'uninitialized'; + my $value = $memfilebytes[$i+$j]; + if ($value eq ""){ + print MEMFILE "00"; + } else { + print MEMFILE "$memfilebytes[$i+$j]"; + } } print MEMFILE "\n"; } @@ -141,5 +188,6 @@ sub fixadr { # strip off leading 8 from address and convert to decimal # if the leading 8 is not present don't remove. my $adr = shift; + #print "addr $adr\n"; return hex($adr); } diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index bd053750c..030c4381b 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -66,18 +66,18 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMBASE 32'h00080000 +`define BOOTTIMBASE 32'h00800000 `define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h00000000 -`define TIMRANGE 32'h0007FFFF -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define TIMRANGE 32'h007FFFFF +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 +`define PLICBASE 32'h0C000000 +`define PLICRANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index ede2da62e..88e228919 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -56,15 +56,14 @@ add wave -noupdate -group Bpred -expand -group direction -group other /testbench add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/DoForwardingF add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRD add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE -add wave -noupdate -group Bpred -group {bp wrong} -divider pcs -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE +add wave -noupdate -group Bpred -expand -group {bp wrong} -divider pcs +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE add wave -noupdate -group Bpred -expand -group BTB -divider Update add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC @@ -96,25 +95,25 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 -add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 -add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW -add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW -add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW -add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW -add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW +add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -group {Decode Stage} /testbench/InstrDName +add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD +add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD +add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D +add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D +add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol @@ -128,10 +127,11 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate /testbench/InstrFName -add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM -add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM -add wave -noupdate -group dcache /testbench/dut/hart/WriteDataM -add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemRWM +add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM +add wave -noupdate -expand -group dcache -radix hexadecimal /testbench/dut/hart/MemPAdrM +add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM +add wave -noupdate -expand -group dcache /testbench/dut/hart/ReadDataW +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -150,15 +150,15 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALURe add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/hart/PCF -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/hart/PCE -add wave -noupdate -group PCS /testbench/dut/hart/PCM -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCW -add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext0F -add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext1F +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW +add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext0F +add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext1F add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate -group {function radix debug} -radix unsigned /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/reset @@ -173,15 +173,53 @@ add wave -noupdate -group {function radix debug} /testbench/FunctionName/Functio add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN -add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW -add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW +add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN +add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW +add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultW add wave -noupdate /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/CSRCReadValM +add wave -noupdate -radix unsigned /testbench/dut/imem/adrbits +add wave -noupdate /testbench/dut/imem/rd +add wave -noupdate /testbench/dut/imem/AdrF +add wave -noupdate /testbench/dut/imem/InstrF +add wave -noupdate /testbench/dut/InstrF +add wave -noupdate /testbench/dut/InstrF +add wave -noupdate -divider {New Divider} +add wave -noupdate /testbench/dut/hart/ifu/InstrInF +add wave -noupdate /testbench/dut/hart/ifu/rd2 +add wave -noupdate /testbench/dut/hart/InstrRData +add wave -noupdate /testbench/dut/hart/rd2 +add wave -noupdate /testbench/dut/hart/ebu/InstrRData +add wave -noupdate /testbench/dut/hart/ebu/InstrPAdrF +add wave -noupdate /testbench/dut/hart/ebu/HRDATA +add wave -noupdate /testbench/dut/uncore/HSELUARTD +add wave -noupdate /testbench/dut/uncore/HSELUART +add wave -noupdate /testbench/dut/uncore/HSELTimD +add wave -noupdate /testbench/dut/uncore/HSELTim +add wave -noupdate /testbench/dut/uncore/HSELPLICD +add wave -noupdate /testbench/dut/uncore/HSELPLIC +add wave -noupdate /testbench/dut/uncore/HSELGPIOD +add wave -noupdate /testbench/dut/uncore/HSELGPIO +add wave -noupdate /testbench/dut/uncore/HSELCLINTD +add wave -noupdate /testbench/dut/uncore/HSELCLINT +add wave -noupdate /testbench/dut/uncore/HSELBootTimD +add wave -noupdate /testbench/dut/uncore/HSELBootTim +add wave -noupdate /testbench/dut/uncore/HREADTim +add wave -noupdate /testbench/dut/uncore/dtim/HREADTim +add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0 +add wave -noupdate /testbench/dut/uncore/dtim/BASE +add wave -noupdate /testbench/dut/uncore/dtim/RANGE +add wave -noupdate /testbench/memfilename +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[770056]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[771306]} +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR +add wave -noupdate /testbench/dut/uncore/dtim/RAM +add wave -noupdate /testbench/dut/uncore/dtim/HREADTim +add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0 TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {13518 ns} 0} +WaveRestoreCursors {{Cursor 7} {15047768 ns} 0} {{Cursor 2} {34763538 ns} 0} {{Cursor 3} {15046271 ns} 0} {{Cursor 4} {15047307 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 229 @@ -197,4 +235,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {13489 ns} {13607 ns} +WaveRestoreZoom {15047734 ns} {15047902 ns} diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index c9c5919a7..c11b805a3 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -317,6 +317,7 @@ string tests32i[] = { string testsBP64[] = '{ "rv64BP/simple", "10000", + "rv64BP/qsort", "1000000", "rv64BP/sieve", "1000000" }; string tests[];