Icache ITLB interlock fix.

wally-pipelined/src/cache/ICacheCntrl.sv

@@ -56,6 +56,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
 
     // Outputs to pipeline control stuff
     output logic 		ICacheStallF, EndFetchState,
+    input logic  ITLBMissF,
+    input logic  ITLBWriteF,
 
     // Signals to/from ahblite interface
     // A read containing the requested data
@@ -109,6 +111,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
   
 
   localparam STATE_INVALIDATE = 18; // *** not sure if invalidate or evict? invalidate by cache block or address?
+  localparam STATE_TLB_MISS = 19;
+  localparam STATE_TLB_MISS_DONE = 20;
+  
+  
   
   localparam AHBByteLength = `XLEN / 8;
   localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
@@ -209,7 +215,9 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
       STATE_READY: begin
 	PCMux = 2'b00;
 	ICacheReadEn = 1'b1;
-	if (hit & ~spill) begin
+	if (ITLBMissF) begin
+	  NextState = STATE_TLB_MISS;
+	end else if (hit & ~spill) begin
 	  SavePC = 1'b1;
 	  ICacheStallF = 1'b0;
 	  NextState = STATE_READY;
@@ -363,6 +371,16 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
 	ICacheStallF = 1'b0;	
 	NextState = STATE_READY;
       end
+      STATE_TLB_MISS: begin
+	if (ITLBWriteF) begin
+	  NextState = STATE_TLB_MISS_DONE;
+	end else begin
+	  NextState = STATE_TLB_MISS;
+	end
+      end
+      STATE_TLB_MISS_DONE : begin
+	NextState = STATE_READY;
+      end
       default: begin
 	PCMux = 2'b01;
 	NextState = STATE_READY;

wally-pipelined/src/cache/icache.sv

@@ -43,6 +43,9 @@ module icache
    output logic 	       CompressedF,
    // High if the icache is requesting a stall
    output logic 	       ICacheStallF,
+   input logic 		       ITLBMissF,
+   input logic 		       ITLBWriteF,
+   
    // The raw (not decompressed) instruction that was requested
    // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
    output logic [31:0] 	       FinalInstrRawF