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uncore cleanup

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This commit is contained in:
David Harris 2023-01-14 17:21:07 -08:00
parent 16ff590a8c
commit be029deb07
5 changed files with 64 additions and 75 deletions
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49
pipelined/src/uncore/ahbapbbridge.sv
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@ -28,34 +28,33 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbapbbridge #(PERIPHS = 2) ( module ahbapbbridge #(PERIPHS = 2) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic [PERIPHS-1:0] HSEL, input logic [PERIPHS-1:0] HSEL,
input logic [`PA_BITS-1:0] HADDR, input logic [`PA_BITS-1:0] HADDR,
input logic [`XLEN-1:0] HWDATA, input logic [`XLEN-1:0] HWDATA,
input logic [`XLEN/8-1:0] HWSTRB, input logic [`XLEN/8-1:0] HWSTRB,
input logic HWRITE, input logic HWRITE,
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
input logic HREADY, input logic HREADY,
// input logic [3:0] HPROT, // not used // input logic [3:0] HPROT, // not used
output logic [`XLEN-1:0] HRDATA, output logic [`XLEN-1:0] HRDATA,
output logic HRESP, HREADYOUT, output logic HRESP, HREADYOUT,
output logic PCLK, PRESETn, output logic PCLK, PRESETn,
output logic [PERIPHS-1:0] PSEL, output logic [PERIPHS-1:0] PSEL,
output logic PWRITE, output logic PWRITE,
output logic PENABLE, output logic PENABLE,
output logic [31:0] PADDR, output logic [31:0] PADDR,
output logic [`XLEN-1:0] PWDATA, output logic [`XLEN-1:0] PWDATA,
// output logic [2:0] PPROT, // not used // output logic [2:0] PPROT, // not used
output logic [`XLEN/8-1:0] PSTRB, output logic [`XLEN/8-1:0] PSTRB,
// output logic PWAKEUP // not used // output logic PWAKEUP // not used
input logic [PERIPHS-1:0] PREADY, input logic [PERIPHS-1:0] PREADY,
input var [PERIPHS-1:0][`XLEN-1:0] PRDATA input var [PERIPHS-1:0][`XLEN-1:0] PRDATA
); );
logic initTrans, initTransSel, initTransSelD;
logic initTrans, initTransSel, initTransSelD; logic nextPENABLE;
logic nextPENABLE; logic PREADYOUT;
logic PREADYOUT;
// convert AHB to APB signals // convert AHB to APB signals
assign PCLK = HCLK; assign PCLK = HCLK;

30
pipelined/src/uncore/clint_apb.sv
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@ -30,24 +30,24 @@
`include "wally-config.vh" `include "wally-config.vh"
module clint_apb ( module clint_apb (
input logic PCLK, PRESETn, input logic PCLK, PRESETn,
input logic PSEL, input logic PSEL,
input logic [15:0] PADDR, input logic [15:0] PADDR,
input logic [`XLEN-1:0] PWDATA, input logic [`XLEN-1:0] PWDATA,
input logic [`XLEN/8-1:0] PSTRB, input logic [`XLEN/8-1:0] PSTRB,
input logic PWRITE, input logic PWRITE,
input logic PENABLE, input logic PENABLE,
output logic [`XLEN-1:0] PRDATA, output logic [`XLEN-1:0] PRDATA,
output logic PREADY, output logic PREADY,
(* mark_debug = "true" *) output logic [63:0] MTIME, (* mark_debug = "true" *) output logic [63:0] MTIME,
output logic MTimerInt, MSwInt); output logic MTimerInt, MSwInt
);
logic MSIP; logic MSIP;
logic [15:0] entry;
logic [15:0] entry; logic memwrite;
logic memwrite;
(* mark_debug = "true" *) logic [63:0] MTIMECMP; (* mark_debug = "true" *) logic [63:0] MTIMECMP;
integer i, j; integer i, j;
assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond

40
pipelined/src/uncore/gpio_apb.sv
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@ -31,28 +31,28 @@
`include "wally-config.vh" `include "wally-config.vh"
module gpio_apb ( module gpio_apb (
input logic PCLK, PRESETn, input logic PCLK, PRESETn,
input logic PSEL, input logic PSEL,
input logic [7:0] PADDR, input logic [7:0] PADDR,
input logic [`XLEN-1:0] PWDATA, input logic [`XLEN-1:0] PWDATA,
input logic [`XLEN/8-1:0] PSTRB, input logic [`XLEN/8-1:0] PSTRB,
input logic PWRITE, input logic PWRITE,
input logic PENABLE, input logic PENABLE,
output logic [`XLEN-1:0] PRDATA, output logic [`XLEN-1:0] PRDATA,
output logic PREADY, output logic PREADY,
input logic [31:0] iof0, iof1, input logic [31:0] iof0, iof1,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn, output logic [31:0] GPIOPinsOut, GPIOPinsEn,
output logic GPIOIntr); output logic GPIOIntr
);
logic [31:0] input0d, input1d, input2d, input3d; logic [31:0] input0d, input1d, input2d, input3d;
logic [31:0] input_val, input_en, output_en, output_val; logic [31:0] input_val, input_en, output_en, output_val;
logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip;
logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out; logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out;
logic [7:0] entry;
logic [7:0] entry; logic [31:0] Din, Dout;
logic [31:0] Din, Dout; logic memwrite;
logic memwrite;
// APB I/O // APB I/O
assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses

7
pipelined/src/uncore/plic_apb.sv
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@ -38,11 +38,11 @@
`define N `PLIC_NUM_SRC `define N `PLIC_NUM_SRC
// number of interrupt sources // number of interrupt sources
// does not include source 0, which does not connect to anything according to spec // does not include source 0, which does not connect to anything according to spec
// up to 63 sources supported; *** in the future, allow up to 1023 sources // up to 63 sources supported; in the future, allow up to 1023 sources
`define C 2 `define C 2
// number of conexts // number of conexts
// hardcoded to 2 contexts for now; *** later upgrade to arbitrary (up to 15872) contexts // hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts
module plic_apb ( module plic_apb (
input logic PCLK, PRESETn, input logic PCLK, PRESETn,
@ -55,7 +55,8 @@ module plic_apb (
output logic [`XLEN-1:0] PRDATA, output logic [`XLEN-1:0] PRDATA,
output logic PREADY, output logic PREADY,
input logic UARTIntr,GPIOIntr, input logic UARTIntr,GPIOIntr,
(* mark_debug = "true" *) output logic MExtInt, SExtInt); (* mark_debug = "true" *) output logic MExtInt, SExtInt
);
logic memwrite, memread; logic memwrite, memread;
logic [23:0] entry; logic [23:0] entry;

13
pipelined/src/uncore/uart_apb.sv
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@ -33,7 +33,7 @@
module uart_apb ( module uart_apb (
input logic PCLK, PRESETn, input logic PCLK, PRESETn,
input logic PSEL, input logic PSEL,
input logic [2:0] PADDR, input logic [2:0] PADDR,
input logic [`XLEN-1:0] PWDATA, input logic [`XLEN-1:0] PWDATA,
input logic [`XLEN/8-1:0] PSTRB, input logic [`XLEN/8-1:0] PSTRB,
input logic PWRITE, input logic PWRITE,
@ -56,17 +56,6 @@ module uart_apb (
assign MEMRb = ~memread; assign MEMRb = ~memread;
assign MEMWb = ~memwrite; assign MEMWb = ~memwrite;
/*
// rename processor interface signals to match PC16550D and provide one-byte interface
flopr #(1) memreadreg(HCLK, ~HRESETn, (HSELUART & ~HWRITE), memread);
flopr #(1) memwritereg(HCLK, ~HRESETn, (HSELUART & HWRITE), memwrite);
flopr #(3) haddrreg(HCLK, ~HRESETn, HADDR[2:0], A);
assign MEMRb = ~memread;
assign MEMWb = ~memwrite;
assign HRESPUART = 0; // OK
assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something
*/
if (`XLEN == 64) begin:uart if (`XLEN == 64) begin:uart
always_comb begin always_comb begin
PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};