From be029deb0772a357bb4cc8372465761227243cc8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 14 Jan 2023 17:21:07 -0800 Subject: [PATCH] uncore cleanup --- pipelined/src/uncore/ahbapbbridge.sv | 49 ++++++++++++++-------------- pipelined/src/uncore/clint_apb.sv | 30 ++++++++--------- pipelined/src/uncore/gpio_apb.sv | 40 +++++++++++------------ pipelined/src/uncore/plic_apb.sv | 7 ++-- pipelined/src/uncore/uart_apb.sv | 13 +------- 5 files changed, 64 insertions(+), 75 deletions(-) diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv index 44a2335fd..011356ba2 100644 --- a/pipelined/src/uncore/ahbapbbridge.sv +++ b/pipelined/src/uncore/ahbapbbridge.sv @@ -28,34 +28,33 @@ `include "wally-config.vh" module ahbapbbridge #(PERIPHS = 2) ( - input logic HCLK, HRESETn, - input logic [PERIPHS-1:0] HSEL, - input logic [`PA_BITS-1:0] HADDR, - input logic [`XLEN-1:0] HWDATA, - input logic [`XLEN/8-1:0] HWSTRB, - input logic HWRITE, - input logic [1:0] HTRANS, - input logic HREADY, -// input logic [3:0] HPROT, // not used - output logic [`XLEN-1:0] HRDATA, - output logic HRESP, HREADYOUT, - output logic PCLK, PRESETn, - output logic [PERIPHS-1:0] PSEL, - output logic PWRITE, - output logic PENABLE, - output logic [31:0] PADDR, - output logic [`XLEN-1:0] PWDATA, -// output logic [2:0] PPROT, // not used - output logic [`XLEN/8-1:0] PSTRB, -// output logic PWAKEUP // not used - input logic [PERIPHS-1:0] PREADY, + input logic HCLK, HRESETn, + input logic [PERIPHS-1:0] HSEL, + input logic [`PA_BITS-1:0] HADDR, + input logic [`XLEN-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, + input logic HWRITE, + input logic [1:0] HTRANS, + input logic HREADY, +// input logic [3:0] HPROT, // not used + output logic [`XLEN-1:0] HRDATA, + output logic HRESP, HREADYOUT, + output logic PCLK, PRESETn, + output logic [PERIPHS-1:0] PSEL, + output logic PWRITE, + output logic PENABLE, + output logic [31:0] PADDR, + output logic [`XLEN-1:0] PWDATA, +// output logic [2:0] PPROT, // not used + output logic [`XLEN/8-1:0] PSTRB, +// output logic PWAKEUP // not used + input logic [PERIPHS-1:0] PREADY, input var [PERIPHS-1:0][`XLEN-1:0] PRDATA ); - - logic initTrans, initTransSel, initTransSelD; - logic nextPENABLE; - logic PREADYOUT; + logic initTrans, initTransSel, initTransSelD; + logic nextPENABLE; + logic PREADYOUT; // convert AHB to APB signals assign PCLK = HCLK; diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv index ba9ecc7cc..6784a2a3e 100644 --- a/pipelined/src/uncore/clint_apb.sv +++ b/pipelined/src/uncore/clint_apb.sv @@ -30,24 +30,24 @@ `include "wally-config.vh" module clint_apb ( - input logic PCLK, PRESETn, - input logic PSEL, - input logic [15:0] PADDR, - input logic [`XLEN-1:0] PWDATA, - input logic [`XLEN/8-1:0] PSTRB, - input logic PWRITE, - input logic PENABLE, - output logic [`XLEN-1:0] PRDATA, - output logic PREADY, + input logic PCLK, PRESETn, + input logic PSEL, + input logic [15:0] PADDR, + input logic [`XLEN-1:0] PWDATA, + input logic [`XLEN/8-1:0] PSTRB, + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, (* mark_debug = "true" *) output logic [63:0] MTIME, - output logic MTimerInt, MSwInt); + output logic MTimerInt, MSwInt +); - logic MSIP; - - logic [15:0] entry; - logic memwrite; + logic MSIP; + logic [15:0] entry; + logic memwrite; (* mark_debug = "true" *) logic [63:0] MTIMECMP; - integer i, j; + integer i, j; assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv index 475d5c85e..7a8ac3c14 100644 --- a/pipelined/src/uncore/gpio_apb.sv +++ b/pipelined/src/uncore/gpio_apb.sv @@ -31,28 +31,28 @@ `include "wally-config.vh" module gpio_apb ( - input logic PCLK, PRESETn, - input logic PSEL, - input logic [7:0] PADDR, - input logic [`XLEN-1:0] PWDATA, + input logic PCLK, PRESETn, + input logic PSEL, + input logic [7:0] PADDR, + input logic [`XLEN-1:0] PWDATA, input logic [`XLEN/8-1:0] PSTRB, - input logic PWRITE, - input logic PENABLE, - output logic [`XLEN-1:0] PRDATA, - output logic PREADY, - input logic [31:0] iof0, iof1, - input logic [31:0] GPIOPinsIn, - output logic [31:0] GPIOPinsOut, GPIOPinsEn, - output logic GPIOIntr); + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, + input logic [31:0] iof0, iof1, + input logic [31:0] GPIOPinsIn, + output logic [31:0] GPIOPinsOut, GPIOPinsEn, + output logic GPIOIntr +); - logic [31:0] input0d, input1d, input2d, input3d; - logic [31:0] input_val, input_en, output_en, output_val; - logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; - logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out; - - logic [7:0] entry; - logic [31:0] Din, Dout; - logic memwrite; + logic [31:0] input0d, input1d, input2d, input3d; + logic [31:0] input_val, input_en, output_en, output_val; + logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; + logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out; + logic [7:0] entry; + logic [31:0] Din, Dout; + logic memwrite; // APB I/O assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index 6c90e65ea..34b3c75cf 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -38,11 +38,11 @@ `define N `PLIC_NUM_SRC // number of interrupt sources // does not include source 0, which does not connect to anything according to spec -// up to 63 sources supported; *** in the future, allow up to 1023 sources +// up to 63 sources supported; in the future, allow up to 1023 sources `define C 2 // number of conexts -// hardcoded to 2 contexts for now; *** later upgrade to arbitrary (up to 15872) contexts +// hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts module plic_apb ( input logic PCLK, PRESETn, @@ -55,7 +55,8 @@ module plic_apb ( output logic [`XLEN-1:0] PRDATA, output logic PREADY, input logic UARTIntr,GPIOIntr, - (* mark_debug = "true" *) output logic MExtInt, SExtInt); + (* mark_debug = "true" *) output logic MExtInt, SExtInt +); logic memwrite, memread; logic [23:0] entry; diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index 09df23569..916f61687 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -33,7 +33,7 @@ module uart_apb ( input logic PCLK, PRESETn, input logic PSEL, - input logic [2:0] PADDR, + input logic [2:0] PADDR, input logic [`XLEN-1:0] PWDATA, input logic [`XLEN/8-1:0] PSTRB, input logic PWRITE, @@ -56,17 +56,6 @@ module uart_apb ( assign MEMRb = ~memread; assign MEMWb = ~memwrite; -/* - // rename processor interface signals to match PC16550D and provide one-byte interface - flopr #(1) memreadreg(HCLK, ~HRESETn, (HSELUART & ~HWRITE), memread); - flopr #(1) memwritereg(HCLK, ~HRESETn, (HSELUART & HWRITE), memwrite); - flopr #(3) haddrreg(HCLK, ~HRESETn, HADDR[2:0], A); - assign MEMRb = ~memread; - assign MEMWb = ~memwrite; - - assign HRESPUART = 0; // OK - assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something -*/ if (`XLEN == 64) begin:uart always_comb begin PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};