BROKEN. Don't use this commit.

Issue running cacheless with bus.

pipelined/config/buildroot/wally-config.vh

@@ -51,8 +51,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/fpga/wally-config.vh

@@ -53,8 +53,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv32e/wally-config.vh

@@ -52,8 +52,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 0
 `define ICACHE 0
 `define VIRTMEM_SUPPORTED 0

pipelined/config/rv32gc/wally-config.vh

@@ -51,8 +51,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv32i/wally-config.vh

@@ -52,8 +52,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv32ic/wally-config.vh

@@ -51,8 +51,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 0
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 0

pipelined/config/rv64BP/wally-config.vh

@@ -53,8 +53,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv64fp/wally-config.vh

@@ -54,8 +54,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv64fpquad/wally-config.vh

@@ -53,8 +53,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv64gc/wally-config.vh

@@ -53,8 +53,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv64i/wally-config.vh

@@ -53,8 +53,7 @@
 // LSU microarchitectural Features
 `define DMEM 0
 `define IROM 0
-`define DBUS 1
+`define BUS 1
-`define IBUS 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1

pipelined/config/rv64ic/wally-config.vh

@@ -53,8 +53,7 @@
 // LSU microarchitectural Features
 `define DMEM 1
 `define IROM 1
-`define DBUS 1
+`define BUS 0
-`define IBUS 1
 `define DCACHE 0
 `define ICACHE 0
 `define VIRTMEM_SUPPORTED 0

pipelined/src/ifu/ifu.sv

@@ -192,7 +192,7 @@ module ifu (
     assign {BusStall, IFUBusRead} = '0;   
     assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
   end 
-  if (`IBUS) begin : bus
+  if (`BUS) begin : bus
     localparam integer   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
     localparam integer   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;

pipelined/src/lsu/lsu.sv

@@ -210,7 +210,7 @@ module lsu (
     assign {DCacheStallM, DCacheCommittedM} = '0;
     assign {DCacheMiss, DCacheAccess} = '0;
   end 
-  if (`DBUS) begin : bus  
+  if (`BUS) begin : bus  
     localparam integer   WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
     localparam integer   LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1;

pipelined/src/wally/wallypipelinedcore.sv

@@ -292,7 +292,7 @@ module wallypipelinedcore (
 
    // *** Ross: please make EBU conditional when only supporting internal memories
 
-  if(`DBUS | `IBUS) begin : ebu
+  if(`BUS) begin : ebu
     ahblite ebu(// IFU connections
      .clk, .reset,
      .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),

pipelined/src/wally/wallypipelinedsoc.sv

@@ -93,7 +93,7 @@ module wallypipelinedsoc (
     .HADDRD, .HSIZED, .HWRITED
    );
 
-  if (`DBUS | `IBUS) begin : uncore
+  if (`BUS) begin : uncore
     uncore uncore(.HCLK, .HRESETn, .TIMECLK,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED, .HSELEXT,

pipelined/testbench/testbench.sv

@@ -233,7 +233,7 @@ logic [3:0] dummy;
         force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       end else begin
         if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
-        else       $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+        else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
         if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
       end
 
@@ -459,8 +459,8 @@ module riscvassertions;
     //    assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
     assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
     assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
+    //assert (`DCACHE == 1 & `BUS ==0) else $error("Dcache requires DBUS.");
-    //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");    
+    //assert (`ICACHE == 1 & `BUS ==0) else $error("Icache requires IBUS.");    
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
   end