diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 1488e528a..cb6658b1c 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -51,8 +51,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 58e425b3b..76b587924 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 19098a0a1..352554006 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -52,8 +52,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 6c2bdd31e..47991e014 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -51,8 +51,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index c785841d0..78b85286a 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -52,8 +52,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 1cdd10d59..27e4db2ef 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -51,8 +51,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 0 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index f2ca2420e..8af61d884 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 4c7c57ed4..653dd864e 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -54,8 +54,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index f1806e0e6..6a40a6885 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 5696252f8..eef5448b4 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index ea3f74d40..c0477fc62 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 7b3d35234..ddd68f9dc 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 1 `define IROM 1 -`define DBUS 1 -`define IBUS 1 +`define BUS 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c1ac1b8f1..59cdb7b88 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -192,7 +192,7 @@ module ifu ( assign {BusStall, IFUBusRead} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; end - if (`IBUS) begin : bus + if (`BUS) begin : bus localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1b7804d8e..9c68ee17d 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -210,7 +210,7 @@ module lsu ( assign {DCacheStallM, DCacheCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; end - if (`DBUS) begin : bus + if (`BUS) begin : bus localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index e620231aa..508b775dc 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -292,7 +292,7 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories - if(`DBUS | `IBUS) begin : ebu + if(`BUS) begin : ebu ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index e1b642494..b62ee2835 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -93,7 +93,7 @@ module wallypipelinedsoc ( .HADDRD, .HSIZED, .HWRITED ); - if (`DBUS | `IBUS) begin : uncore + if (`BUS) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED, .HSELEXT, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index a423a6995..f7b71288f 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -233,7 +233,7 @@ logic [3:0] dummy; force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); - else $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); end @@ -459,8 +459,8 @@ module riscvassertions; // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); - //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); + //assert (`DCACHE == 1 & `BUS ==0) else $error("Dcache requires DBUS."); + //assert (`ICACHE == 1 & `BUS ==0) else $error("Icache requires IBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); end