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Rough draft removal of duplicate BPBTAWrongE logic.

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Rose Thompson 2024-02-01 16:57:33 -06:00
parent 5f0f8c2d3a
commit bd06a5ff88
2 changed files with 21 additions and 14 deletions
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32
src/ifu/bpred/bpred.sv
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@ -88,15 +88,17 @@ module bpred import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] BPBTAD; logic [P.XLEN-1:0] BPBTAD;
logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
logic BPBranchF, BPJumpF, BPReturnF, BPCallF; logic BPBranchF, BPJumpF, BPReturnF, BPCallF;
logic BPBranchD, BPJumpD, BPReturnD, BPCallD; logic BPBranchD, BPJumpD, BPReturnD, BPCallD;
logic ReturnD, CallD; logic ReturnD, CallD;
logic ReturnE, CallE; logic ReturnE, CallE;
logic BranchM, JumpM, ReturnM, CallM; logic BranchM, JumpM, ReturnM, CallM;
logic BranchW, JumpW, ReturnW, CallW; logic BranchW, JumpW, ReturnW, CallW;
logic BPReturnWrongD; logic BPReturnWrongD;
logic [P.XLEN-1:0] BPBTAE; logic [P.XLEN-1:0] BPBTAE;
logic BPBTAWrongM;
logic PCSrcM;
// Part 1 branch direction prediction // Part 1 branch direction prediction
if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor
@ -144,6 +146,8 @@ module bpred import cvw::*; #(parameter cvw_t P) (
.BranchD, .BranchE, .BranchM, .PCSrcE); .BranchD, .BranchE, .BranchM, .PCSrcE);
end end
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
// Part 2 Branch target address prediction // Part 2 Branch target address prediction
// BTB contains target address for all CFI // BTB contains target address for all CFI
@ -152,6 +156,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
.PCNextF, .PCF, .PCD, .PCE, .PCM, .PCNextF, .PCF, .PCD, .PCE, .PCM,
.BPBTAF, .BPBTAD, .BPBTAE, .BPBTAF, .BPBTAD, .BPBTAE,
.BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}), .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
.BPBTAWrongM,
.IClassWrongM, .IClassWrongE, .IClassWrongM, .IClassWrongE,
.IEUAdrE, .IEUAdrM, .IEUAdrE, .IEUAdrM,
.InstrClassD({CallD, ReturnD, JumpD, BranchD}), .InstrClassD({CallD, ReturnD, JumpD, BranchD}),
@ -196,7 +201,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
if(P.ZIHPM_SUPPORTED) begin if(P.ZIHPM_SUPPORTED) begin
logic [P.XLEN-1:0] RASPCD, RASPCE; logic [P.XLEN-1:0] RASPCD, RASPCE;
logic BTAWrongE, RASPredPCWrongE; logic RASPredPCWrongE;
// performance counters // performance counters
// 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now // 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now
// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
@ -208,14 +213,15 @@ module bpred import cvw::*; #(parameter cvw_t P) (
// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
// both without the above inaccuracies. // both without the above inaccuracies.
// **** use BPBTAWrongM from BTB. // **** use BPBTAWrongM from BTB.
assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
{BPDirPredWrongE, BTAWrongE, RASPredPCWrongE}, {BPDirPredWrongE, RASPredPCWrongE},
{BPDirPredWrongM, BTAWrongM, RASPredPCWrongM}); {BPDirPredWrongM, RASPredPCWrongM});
assign BTAWrongM = BPBTAWrongM & PCSrcM;
end else begin end else begin
assign {BTAWrongM, RASPredPCWrongM} = '0; assign {BTAWrongM, RASPredPCWrongM} = '0;

3
src/ifu/bpred/btb.sv
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@ -39,6 +39,7 @@ module btb import cvw::*; #(parameter cvw_t P,
output logic [P.XLEN-1:0] BPBTAD, output logic [P.XLEN-1:0] BPBTAD,
output logic [P.XLEN-1:0] BPBTAE, output logic [P.XLEN-1:0] BPBTAE,
output logic [3:0] BTBIClassF, // BTB's guess at instruction class output logic [3:0] BTBIClassF, // BTB's guess at instruction class
output logic BPBTAWrongM,
// update // update
input logic IClassWrongM, // BTB's instruction class guess was wrong input logic IClassWrongM, // BTB's instruction class guess was wrong
input logic IClassWrongE, input logic IClassWrongE,
@ -57,7 +58,7 @@ module btb import cvw::*; #(parameter cvw_t P,
logic [P.XLEN-1:0] IEUAdrW; logic [P.XLEN-1:0] IEUAdrW;
logic [P.XLEN-1:0] PCW; logic [P.XLEN-1:0] PCW;
logic BTBWrongE, BPBTAWrongE; logic BTBWrongE, BPBTAWrongE;
logic BTBWrongM, BPBTAWrongM; logic BTBWrongM;
// hashing function for indexing the PC // hashing function for indexing the PC