diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index faf537d91..006a60b1d 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -88,15 +88,17 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
 
   logic [P.XLEN-1:0]        BPBTAD;
 
-  logic                    BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
-  logic                    BPBranchF, BPJumpF, BPReturnF, BPCallF;
-  logic                    BPBranchD, BPJumpD, BPReturnD, BPCallD;
-  logic                    ReturnD, CallD;
-  logic                    ReturnE, CallE;
-  logic                    BranchM, JumpM, ReturnM, CallM;
-  logic                    BranchW, JumpW, ReturnW, CallW;
-  logic                    BPReturnWrongD;
+  logic                     BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
+  logic                     BPBranchF, BPJumpF, BPReturnF, BPCallF;
+  logic                     BPBranchD, BPJumpD, BPReturnD, BPCallD;
+  logic                     ReturnD, CallD;
+  logic                     ReturnE, CallE;
+  logic                     BranchM, JumpM, ReturnM, CallM;
+  logic                     BranchW, JumpW, ReturnW, CallW;
+  logic                     BPReturnWrongD;
   logic [P.XLEN-1:0]        BPBTAE;
+  logic                     BPBTAWrongM;
+  logic                     PCSrcM;
   
   // Part 1 branch direction prediction
   if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor
@@ -144,6 +146,8 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
       .BranchD, .BranchE, .BranchM, .PCSrcE);
   end 
 
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+  
   // Part 2 Branch target address prediction
   // BTB contains target address for all CFI
 
@@ -152,6 +156,7 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
       .PCNextF, .PCF, .PCD, .PCE, .PCM,
       .BPBTAF, .BPBTAD, .BPBTAE,
       .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
+      .BPBTAWrongM,
       .IClassWrongM, .IClassWrongE,
       .IEUAdrE, .IEUAdrM,
       .InstrClassD({CallD, ReturnD, JumpD, BranchD}), 
@@ -196,7 +201,7 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
 
   if(P.ZIHPM_SUPPORTED) begin
     logic [P.XLEN-1:0]       RASPCD, RASPCE;
-    logic                   BTAWrongE, RASPredPCWrongE;  
+    logic                    RASPredPCWrongE;  
     // performance counters
     // 1. class         (class wrong / minstret) (IClassWrongM / csr)                    // Correct now
     // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
@@ -208,14 +213,15 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
     // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
     // both without the above inaccuracies.
     // **** use BPBTAWrongM from BTB.
-    assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
     assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
 
     flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
     flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
-    flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
-      {BPDirPredWrongE, BTAWrongE, RASPredPCWrongE},
-      {BPDirPredWrongM, BTAWrongM, RASPredPCWrongM});
+    flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
+      {BPDirPredWrongE, RASPredPCWrongE},
+      {BPDirPredWrongM, RASPredPCWrongM});
+
+    assign BTAWrongM = BPBTAWrongM & PCSrcM;
     
   end else begin
     assign {BTAWrongM, RASPredPCWrongM} = '0;
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 2d0d30727..448be38d0 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -39,6 +39,7 @@ module btb import cvw::*;  #(parameter cvw_t P,
   output logic [P.XLEN-1:0] BPBTAD,
   output logic [P.XLEN-1:0] BPBTAE,
   output logic [3:0]       BTBIClassF,                  // BTB's guess at instruction class
+  output logic BPBTAWrongM,
   // update
   input  logic             IClassWrongM,                // BTB's instruction class guess was wrong
   input  logic             IClassWrongE,
@@ -57,7 +58,7 @@ module btb import cvw::*;  #(parameter cvw_t P,
   logic [P.XLEN-1:0]        IEUAdrW;
   logic [P.XLEN-1:0]        PCW;
   logic                    BTBWrongE, BPBTAWrongE;
-  logic                    BTBWrongM, BPBTAWrongM;
+  logic                    BTBWrongM;
   
   
   // hashing function for indexing the PC