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sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera

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David Harris 2022-05-03 03:50:41 -07:00
parent 3f2ec0499f
commit bc132c3e20
1 changed files with 4 additions and 4 deletions
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8
pipelined/src/cache/sram1p1rw.sv vendored
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@ -68,23 +68,23 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
end end
end end
if (WM8 > 0) begin /* if (WM8 > 0) begin // handle msbs that aren't a multiple of 8
if (ByteMask[WIDTH/8]) begin if (ByteMask[WIDTH/8]) begin
StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1 StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1
CacheWriteData[WIDTH-1:WIDTH-WM8]; CacheWriteData[WIDTH-1:WIDTH-WM8];
end end
end end */
end end
end end
/* // if not a multiple of 8, MSByte is not 8 bits long. // if not a multiple of 8, MSByte is not 8 bits long.
if(WIDTH%8 != 0) begin if(WIDTH%8 != 0) begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (WriteEnable & ByteMask[WIDTH/8]) begin if (WriteEnable & ByteMask[WIDTH/8]) begin
StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
end end
end end
end */ end
assign ReadData = StoredData[AdrD]; assign ReadData = StoredData[AdrD];
endmodule endmodule