From bc132c3e206843d22cf194524cfa01cfc5abbe68 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 3 May 2022 03:50:41 -0700
Subject: [PATCH] sram1p1rw extra bits are complaining on Tera and VLSI; roll
 back to two always blocks to fix on Tera

---
 pipelined/src/cache/sram1p1rw.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv
index edd6722ec..7b6739686 100644
--- a/pipelined/src/cache/sram1p1rw.sv
+++ b/pipelined/src/cache/sram1p1rw.sv
@@ -68,23 +68,23 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
            StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
         end
       end
-      if (WM8 > 0) begin
+/*      if (WM8 > 0) begin  // handle msbs that aren't a multiple of 8
 	if (ByteMask[WIDTH/8]) begin
 	  StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1 
 	    CacheWriteData[WIDTH-1:WIDTH-WM8];
 	end
-      end
+      end */
     end
   end
   
-/*  // if not a multiple of 8, MSByte is not 8 bits long.
+  // if not a multiple of 8, MSByte is not 8 bits long.
   if(WIDTH%8 != 0) begin
     always_ff @(posedge clk) begin
       if (WriteEnable & ByteMask[WIDTH/8]) begin
         StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
       end
     end
-  end */
+  end 
 
   assign ReadData = StoredData[AdrD];
 endmodule