Fix mmu lint errors

This commit is contained in:
Thomas Fleming 2021-04-13 19:19:58 -04:00
parent e164437fe8
commit bb2d433971
2 changed files with 13 additions and 2 deletions

View File

@ -138,7 +138,6 @@ module pagetablewalker (
localparam LEVEL0 = 3'h2; localparam LEVEL0 = 3'h2;
localparam LEAF = 3'h3; localparam LEAF = 3'h3;
localparam FAULT = 3'h4; localparam FAULT = 3'h4;
localparam LEVEL2 = 3'h5;
logic [2:0] WalkerState, NextWalkerState; logic [2:0] WalkerState, NextWalkerState;
@ -172,6 +171,8 @@ module pagetablewalker (
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
FAULT: if (MMUTranslate) NextWalkerState = LEVEL1; FAULT: if (MMUTranslate) NextWalkerState = LEVEL1;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
// Default case should never happen, but is included for linter.
default: NextWalkerState = IDLE;
endcase endcase
end end
@ -219,6 +220,9 @@ module pagetablewalker (
LoadPageFaultM = DTLBMissM && ~MemStore; LoadPageFaultM = DTLBMissM && ~MemStore;
StorePageFaultM = DTLBMissM && MemStore; StorePageFaultM = DTLBMissM && MemStore;
end end
default: begin
// nothing
end
endcase endcase
end end
@ -233,6 +237,8 @@ module pagetablewalker (
assign MMUPAdr = TranslationPAdr[31:0]; assign MMUPAdr = TranslationPAdr[31:0];
end else begin end else begin
localparam LEVEL2 = 3'h5;
assign SvMode = SATP_REGW[63]; assign SvMode = SATP_REGW[63];
logic [8:0] VPN2, VPN1, VPN0; logic [8:0] VPN2, VPN1, VPN0;
@ -265,6 +271,8 @@ module pagetablewalker (
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
FAULT: if (MMUTranslate) NextWalkerState = LEVEL2; FAULT: if (MMUTranslate) NextWalkerState = LEVEL2;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
// Default case should never happen, but is included for linter.
default: NextWalkerState = IDLE;
endcase endcase
end end
@ -321,6 +329,9 @@ module pagetablewalker (
LoadPageFaultM = DTLBMissM && ~MemStore; LoadPageFaultM = DTLBMissM && ~MemStore;
StorePageFaultM = DTLBMissM && MemStore; StorePageFaultM = DTLBMissM && MemStore;
end end
default: begin
// nothing
end
endcase endcase
end end

View File

@ -71,6 +71,6 @@ module cam_line #(parameter KEY_BITS = 20,
// should automatically match. // should automatically match.
page_number_mixer #(KEY_BITS, HIGH_SEGMENT_BITS) mixer(VirtualPageNumber, Key, PageType, VirtualPageNumberQuery); page_number_mixer #(KEY_BITS, HIGH_SEGMENT_BITS) mixer(VirtualPageNumber, Key, PageType, VirtualPageNumberQuery);
assign Match = ({1'b1, VirtualPageNumberQuery} == Key); assign Match = ({1'b1, VirtualPageNumberQuery} == {Valid, Key});
endmodule endmodule