From bb2d4339714d062be1c612a5504d5ef75a8db6dd Mon Sep 17 00:00:00 2001 From: Thomas Fleming Date: Tue, 13 Apr 2021 19:19:58 -0400 Subject: [PATCH] Fix mmu lint errors --- wally-pipelined/src/ebu/pagetablewalker.sv | 13 ++++++++++++- wally-pipelined/src/mmu/cam_line.sv | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv b/wally-pipelined/src/ebu/pagetablewalker.sv index 884dcd01b..8b3723f4b 100644 --- a/wally-pipelined/src/ebu/pagetablewalker.sv +++ b/wally-pipelined/src/ebu/pagetablewalker.sv @@ -138,7 +138,6 @@ module pagetablewalker ( localparam LEVEL0 = 3'h2; localparam LEAF = 3'h3; localparam FAULT = 3'h4; - localparam LEVEL2 = 3'h5; logic [2:0] WalkerState, NextWalkerState; @@ -172,6 +171,8 @@ module pagetablewalker ( else NextWalkerState = IDLE; FAULT: if (MMUTranslate) NextWalkerState = LEVEL1; else NextWalkerState = IDLE; + // Default case should never happen, but is included for linter. + default: NextWalkerState = IDLE; endcase end @@ -219,6 +220,9 @@ module pagetablewalker ( LoadPageFaultM = DTLBMissM && ~MemStore; StorePageFaultM = DTLBMissM && MemStore; end + default: begin + // nothing + end endcase end @@ -233,6 +237,8 @@ module pagetablewalker ( assign MMUPAdr = TranslationPAdr[31:0]; end else begin + localparam LEVEL2 = 3'h5; + assign SvMode = SATP_REGW[63]; logic [8:0] VPN2, VPN1, VPN0; @@ -265,6 +271,8 @@ module pagetablewalker ( else NextWalkerState = IDLE; FAULT: if (MMUTranslate) NextWalkerState = LEVEL2; else NextWalkerState = IDLE; + // Default case should never happen, but is included for linter. + default: NextWalkerState = IDLE; endcase end @@ -321,6 +329,9 @@ module pagetablewalker ( LoadPageFaultM = DTLBMissM && ~MemStore; StorePageFaultM = DTLBMissM && MemStore; end + default: begin + // nothing + end endcase end diff --git a/wally-pipelined/src/mmu/cam_line.sv b/wally-pipelined/src/mmu/cam_line.sv index e74ac53b8..b75775738 100644 --- a/wally-pipelined/src/mmu/cam_line.sv +++ b/wally-pipelined/src/mmu/cam_line.sv @@ -71,6 +71,6 @@ module cam_line #(parameter KEY_BITS = 20, // should automatically match. page_number_mixer #(KEY_BITS, HIGH_SEGMENT_BITS) mixer(VirtualPageNumber, Key, PageType, VirtualPageNumberQuery); - assign Match = ({1'b1, VirtualPageNumberQuery} == Key); + assign Match = ({1'b1, VirtualPageNumberQuery} == {Valid, Key}); endmodule