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LSU Cleanup

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This commit is contained in:
David Harris 2022-01-15 01:11:17 +00:00
parent f7f3882cb8
commit b967bcede2
4 changed files with 7 additions and 5 deletions
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2
pipelined/regression/regression-wally
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@ -145,7 +145,7 @@ def main():
num_fail+=result.get(timeout=TIMEOUT_DUR) num_fail+=result.get(timeout=TIMEOUT_DUR)
except TimeoutError: except TimeoutError:
num_fail+=1 num_fail+=1
print("%s: Timeout - runtime exceeded %d seconds" % (config.name, TIMEOUT_DUR)) print("%s_%s: Timeout - runtime exceeded %d seconds" % (config.variant, config.name, TIMEOUT_DUR))
# Count the number of failures # Count the number of failures
if num_fail: if num_fail:

2
pipelined/regression/sim-wally
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@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv32gc arch32f" vsim -do "do wally-pipelined.do rv32tim arch32i"

1
pipelined/src/cache/cache.sv vendored
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@ -172,7 +172,6 @@ module cache #(parameter integer LINELEN,
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
// easily build a variable input mux. // easily build a variable input mux.
// *** consider using a limited range shift to do this final muxing.
genvar index; genvar index;
if(DCACHE == 1) begin: readdata if(DCACHE == 1) begin: readdata
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux

7
pipelined/src/lsu/lsu.sv
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@ -210,7 +210,7 @@ module lsu
.Idempotent(), .AtomicAllowed(), .Idempotent(), .AtomicAllowed(),
.TLBPageFault(DTLBPageFaultM), .TLBPageFault(DTLBPageFaultM),
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]), .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
); );
@ -294,7 +294,10 @@ module lsu
// There are no peripherals supported. // There are no peripherals supported.
assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0; assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0;
assign ReadDataWordMuxM = ReadDataWordM; assign ReadDataWordMuxM = ReadDataWordM;
end else begin : bus // *** lsubusdp assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
assign ReadDataLineSetsM[0] = 0;
assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
end else begin : bus // *** lsubusdp
// Bus Side logic // Bus Side logic
// register the fetch data from the next level of memory. // register the fetch data from the next level of memory.
// This register should be necessary for timing. There is no register in the uncore or // This register should be necessary for timing. There is no register in the uncore or