From b967bcede2a58e0df23a1b466a09d7b0eea6bad7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 15 Jan 2022 01:11:17 +0000
Subject: [PATCH] LSU Cleanup

---
 pipelined/regression/regression-wally | 2 +-
 pipelined/regression/sim-wally        | 2 +-
 pipelined/src/cache/cache.sv          | 1 -
 pipelined/src/lsu/lsu.sv              | 7 +++++--
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index b322ebcc2..a8f4f4dd4 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -145,7 +145,7 @@ def main():
              num_fail+=result.get(timeout=TIMEOUT_DUR)
            except TimeoutError:
              num_fail+=1
-             print("%s: Timeout - runtime exceeded %d seconds" % (config.name, TIMEOUT_DUR))
+             print("%s_%s: Timeout - runtime exceeded %d seconds" % (config.variant, config.name, TIMEOUT_DUR))
 
     # Count the number of failures
     if num_fail:
diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally
index a7dffc9ed..ec21b653f 100755
--- a/pipelined/regression/sim-wally
+++ b/pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32gc arch32f"
+vsim -do "do wally-pipelined.do rv32tim arch32i"
 
diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index a7e6dba8d..e10979f27 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -172,7 +172,6 @@ module cache #(parameter integer LINELEN,
 
   // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
   // easily build a variable input mux.
-  // *** consider using a limited range shift to do this final muxing.
   genvar index;
 	if(DCACHE == 1) begin: readdata
     for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 8d2d59faa..db7a689d4 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -210,7 +210,7 @@ module lsu
       .Idempotent(), .AtomicAllowed(),
       .TLBPageFault(DTLBPageFaultM),
       .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
-      .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),  ///  atomicaccessm is probably a bug
+      .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), 
       .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
       );
@@ -294,7 +294,10 @@ module lsu
     // There are no peripherals supported.
     assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0;   
     assign ReadDataWordMuxM = ReadDataWordM;
-  end else begin : bus  // *** lsubusdp
+    assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
+    assign ReadDataLineSetsM[0] = 0;
+    assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
+end else begin : bus  // *** lsubusdp
     // Bus Side logic
     // register the fetch data from the next level of memory.
     // This register should be necessary for timing.  There is no register in the uncore or