diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 9dbc876fa..4ec5a1372 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -27,7 +27,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( +module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, USE_SRAM, READ_ONLY_CACHE) ( input logic clk, input logic reset, input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY @@ -112,7 +112,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W AdrSelMuxSel, CacheSet); // Array of cache ways, along with victim, hit, dirty, and read merging logic - cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( + cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, USE_SRAM, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache); diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 47c3de69c..9687e478a 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26, - OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( + OFFSETLEN = 5, INDEXLEN = 9, USE_SRAM = 1, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) @@ -109,7 +109,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), + ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN), .USE_SRAM(USE_SRAM)) CacheTagMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadTag), .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); @@ -137,7 +137,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end else begin:wordram // no byte-enable needed for i$. - ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), + ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN), .USE_SRAM(USE_SRAM)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn)); diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index 1e906dca8..97e0ac7e4 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flop #(parameter WIDTH = 8) ( input logic clk, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index 32e0d7dd3..2e6432519 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopen #(parameter WIDTH = 8) ( input logic clk, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 094779c74..562c4565a 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( input logic clk, load, en, input TYPE d, diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 3b8129e40..2c2144ab8 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopenr #(parameter WIDTH = 8) ( input logic clk, reset, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index b3d5a1e8e..94b2b3cb0 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopenrc #(parameter WIDTH = 8) ( input logic clk, reset, clear, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index 1f4c18051..c4fc5d01b 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopens #(parameter WIDTH = 8) ( input logic clk, set, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index b2f99b3cd..2e39ee8d6 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopr #(parameter WIDTH = 8) ( input logic clk, reset, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv index 8275a8f96..b35e9ccce 100644 --- a/src/generic/flop/floprc.sv +++ b/src/generic/flop/floprc.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module floprc #(parameter WIDTH = 8) ( input logic clk, input logic reset, diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index f10efaeaf..f99088af4 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module synchronizer ( input logic clk, input logic d, diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 8905cc551..6cd9dae05 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -30,11 +30,11 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words - `include "wally-config.vh" -module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( +// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words + +module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index f3a8a2248..f819ac0ce 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -30,9 +30,7 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -`include "wally-config.vh" - -module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) ( +module ram1p1rwe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -46,19 +44,19 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray + if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); - end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag + end else if ((USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag // 64 x 44-bit SRAM ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); - end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag + end else if ((USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag // 64 x 22-bit SRAM ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 51e2871b4..18ed9d5ea 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -29,11 +29,11 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words - `include "wally-config.vh" -module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( +// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words + +module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, @@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( // TRUE Smem macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin + if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( .QA(rd1), .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin + end else if ((USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index ef9c6da37..497356788 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -25,8 +25,6 @@ // This model actually works correctly with vivado. -`include "wally-config.vh" - module rom1p1r #(parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 32, parameter PRELOAD_ENABLED = 0) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 43df83b60..c3ad75551 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" -module alu #(parameter WIDTH=32) ( +module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) ( input logic [WIDTH-1:0] A, B, // Operands input logic W64, // W64-type instruction input logic SubArith, // Subtraction or arithmetic shift @@ -56,7 +56,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); + shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -76,7 +76,7 @@ module alu #(parameter WIDTH=32) ( 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) + 3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr endcase @@ -87,8 +87,8 @@ module alu #(parameter WIDTH=32) ( else assign PreALUResult = FullResult; // Final Result B instruction select mux - if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, + if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu + bitmanipalu #(P, WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin @@ -96,4 +96,4 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = B; assign CondShiftA = A; end -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index d3094377d..75b8bed02 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -27,9 +27,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module bitmanipalu #(parameter WIDTH=32) ( +module bitmanipalu import cvw::*; #(parameter cvw_t P, + parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic W64, // W64-type instruction input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction @@ -56,13 +55,13 @@ module bitmanipalu #(parameter WIDTH=32) ( assign {Mask, PreShift} = BALUControl[1:0]; // Mask Generation Mux - if (`ZBS_SUPPORTED) begin: zbsdec + if (P.ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; // 0-3 bit Pre-Shift Mux - if (`ZBA_SUPPORTED) begin: zbapreshift + if (P.ZBA_SUPPORTED) begin: zbapreshift if (WIDTH == 64) begin mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA); end else assign CondZextA = A; @@ -74,12 +73,12 @@ module bitmanipalu #(parameter WIDTH=32) ( end // Bit reverse needed for some ZBB, ZBC instructions - if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse + if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.A, .RevA); end // ZBC Unit - if (`ZBC_SUPPORTED) begin: zbc + if (P.ZBC_SUPPORTED) begin: zbc logic ZBCSelect; // ZBC instruction assign ZBCSelect = BSelect == 2'b11; //assign ZBCSelect = 1'b0; @@ -87,7 +86,7 @@ module bitmanipalu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; // ZBB Unit - if (`ZBB_SUPPORTED) begin: zbb + if (P.ZBB_SUPPORTED) begin: zbb zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index e2afb0c95..fc2530aab 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -27,7 +27,6 @@ // either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" module bitreverse #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index e6099533b..2879ba042 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module byteop #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands input logic ByteSelect, // LSB of Immediate @@ -43,4 +41,4 @@ module byteop #(parameter WIDTH=32) ( end mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index cf3e1c6b1..675387577 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] X, Y, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index a1f82eb7e..d015c1195 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -28,8 +28,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module cnt #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, RevA, // Operands input logic [1:0] B, // Last 2 bits of immediate @@ -62,4 +60,4 @@ module cnt #(parameter WIDTH = 32) ( assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0; mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 438addaa8..1feca6e1e 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -28,8 +28,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module ext #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, // Operands input logic [1:0] ExtSelect, // B[2], B[0] of immediate @@ -42,4 +40,4 @@ module ext #(parameter WIDTH = 32) ( assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 3d7bcedd9..9ae3df42d 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -28,8 +28,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands input logic W64, // Indicates word operation @@ -55,4 +53,4 @@ module zbb #(parameter WIDTH=32) ( // ZBB Result select mux mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 30f65258f..9ecbde3ca 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module zbc #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands input logic ZBCSelect, // ZBC instruction diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 5f504dced..0803d8b2f 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // This comparator is best module comparator #(parameter WIDTH=64) ( input logic [WIDTH-1:0] a, b, // Operands diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index cb013ee9d..0c315dbdb 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -112,7 +112,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE); + alu #(P, P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE); mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 11ae1cf0a..40dd7d788 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -27,21 +27,19 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module shifter ( - input logic [`XLEN-1:0] A, // shift Source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount +module shifter import cvw::*; #(parameter cvw_t P) ( + input logic [P.XLEN-1:0] A, // shift Source + input logic [P.LOG_XLEN-1:0] Amt, // Shift amount input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift - output logic [`XLEN-1:0] Y); // Shifted result + output logic [P.XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*P.XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [P.LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount logic Sign; // Sign bit for sign extension - assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension - if (`XLEN==32) begin // rv32 - if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates + assign Sign = A[P.XLEN-1] & SubArith; // sign bit for sign extension + if (P.XLEN==32) begin // rv32 + if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates always_comb // funnel mux case({Right, Rotate}) 2'b00: Z = {A[31:0], 31'b0}; @@ -56,12 +54,12 @@ module shifter ( end assign TruncAmt = Amt; // shift amount end else begin // rv64 - logic [`XLEN-1:0] A64; + logic [P.XLEN-1:0] A64; mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux - if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates + if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates // shifter rotate source select mux - logic [`XLEN-1:0] RotA; // rotate source - mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons + logic [P.XLEN-1:0] RotA; // rotate source + mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) 2'b00: Z = {A64[63:0],{63'b0}}; @@ -82,7 +80,7 @@ module shifter ( // Funnel operation assign ZShift = Z >> Offset; - assign Y = ZShift[`XLEN-1:0]; + assign Y = ZShift[P.XLEN-1:0]; endmodule diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 5279f867a..d0e4db45e 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -92,7 +92,7 @@ module btb import cvw::*; #(parameter cvw_t P, // An optimization may be using a PC relative address. - ram2p1r1wbe #(2**Depth, P.XLEN+4) memory( + ram2p1r1wbe #(2**Depth, P.XLEN+4, P.USE_SRAM) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF), .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1)); diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index dcd94e2a2..640ddb273 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -30,7 +30,8 @@ module gshare #(parameter XLEN, parameter k = 10, - parameter integer TYPE = 1) ( + parameter integer TYPE = 1, + parameter USE_SRAM = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -83,7 +84,7 @@ module gshare #(parameter XLEN, assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableBPDirPredF), diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 165915ce2..636e5408c 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -29,7 +29,8 @@ module gsharebasic #(parameter XLEN, parameter k = 10, - parameter TYPE = 1) ( + parameter TYPE = 1, + parameter USE_SRAM = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -57,7 +58,7 @@ module gsharebasic #(parameter XLEN, assign IndexM = GHRM; end - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 6fdf7c3f5..2ba9ef960 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -27,7 +27,8 @@ module localaheadbp #(parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10) ( // number of past branches stored + parameter k = 10, + parameter USE_SRAM = 1) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -58,7 +59,7 @@ module localaheadbp #(parameter XLEN, //assign IndexNextF = LHR; assign IndexM = LHRW; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -91,7 +92,7 @@ module localaheadbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k) BHT(.clk(clk), + ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRF), diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index 827b756e6..1fc302d1c 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -28,7 +28,8 @@ module localbpbasic #(parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10) ( // number of past branches stored + parameter k = 10, + parameter USE_SRAM = 1) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -55,7 +56,7 @@ module localbpbasic #(parameter XLEN, assign IndexNextF = LHR; assign IndexM = LHRM; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index f7be7e71e..835096452 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -27,7 +27,8 @@ module localrepairbp #(parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10) ( // number of past branches stored + parameter k = 10, + parameter USE_SRAM = 1) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -57,7 +58,7 @@ module localrepairbp #(parameter XLEN, logic SpeculativeFlushedF; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -88,7 +89,7 @@ module localrepairbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k) BHT(.clk(clk), + ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRCommittedF), diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 7cb3f4173..aeae77f14 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -27,7 +27,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module twoBitPredictor #(parameter XLEN, - parameter k = 10) ( + parameter k = 10, + parameter USE_SRAM = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -53,7 +54,7 @@ module twoBitPredictor #(parameter XLEN, assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 582dbecbe..c2088ae67 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -29,7 +29,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" module decompress #(parameter XLEN)( input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half @@ -91,18 +90,18 @@ module decompress #(parameter XLEN)( end 5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld 5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw - 5'b00011: if (`XLEN==32) + 5'b00011: if (XLEN==32) InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw else InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld; 5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd 5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw - 5'b00111: if (`XLEN==32) + 5'b00111: if (XLEN==32) InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw else InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd 5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi - 5'b01001: if (`XLEN==32) + 5'b01001: if (XLEN==32) InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal else InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw @@ -126,7 +125,7 @@ module decompress #(parameter XLEN)( InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or else // if (instr16[6:5] == 2'b11) InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and - else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] + else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] if (instr16[6:5] == 2'b00) InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw else if (instr16[6:5] == 2'b01) @@ -151,7 +150,7 @@ module decompress #(parameter XLEN)( 5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli 5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp 5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp - 5'b10011: if (`XLEN == 32) + 5'b10011: if (XLEN == 32) InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp else InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp @@ -170,7 +169,7 @@ module decompress #(parameter XLEN)( InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add 5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp 5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp - 5'b10111: if (`XLEN==32) + 5'b10111: if (XLEN==32) InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp else InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index f33c150d0..571b2121d 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -234,7 +234,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), - .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) + .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(1)) icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 27eaa4107..4a04d51e1 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -29,8 +29,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module spill import cvw::*; #(parameter cvw_t P) ( input logic clk, input logic reset, diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 36b3af1a3..8ee5d3174 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -49,7 +49,7 @@ module dtim import cvw::*; #(parameter cvw_t P) ( assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. - ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN)) + ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN), .USE_SRAM(P.USE_SRAM)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 595f1eec4..02a88beb4 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -262,7 +262,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW); cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( + .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), diff --git a/src/mdu/div.sv b/src/mdu/div.sv index a05e88f6d..a2d7f893d 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -105,7 +105,7 @@ module div import cvw::*; #(parameter cvw_t P) ( // one copy of divstep for each bit produced per cycle genvar i; for (i=0; i XLEN because AHB bus width is XLEN"); - assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN || `DCACHE_SUPPORTED || `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 || (!`DCACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 || (!`ICACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); - assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (`VIRTMEM_SUPPORTED == 0 || (`DTIM_SUPPORTED == 0 && `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE_SUPPORTED == 0 && `ICACHE_SUPPORTED == 0) || `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); - assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE_SUPPORTED || (`A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); - assert (`IDIV_ON_FPU == 0 || `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - assert (`SSTC_SUPPORTED == 0 || (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); - assert ((`ZMMUL_SUPPORTED == 0) || (`M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); + assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); + assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); + assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); + assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); + assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported"); + assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); + assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); + assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); + assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); + assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); + assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); + assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); + assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); + assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); + assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); + assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); + assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); end endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 04e41b158..1b95b5cc4 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -88,7 +88,7 @@ module testbench; logic SelectTest; // check assertions for a legal configuration - riscvassertions riscvassertions(); + riscvassertions #(P) riscvassertions(); // pick tests based on modes supported initial begin