mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed spacing
This commit is contained in:
parent
872f9ed9cc
commit
b8570c4bef
@ -29,21 +29,21 @@
|
|||||||
module fmaadd import cvw::*; #(parameter cvw_t P) (
|
module fmaadd import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic [3*P.NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
|
input logic [3*P.NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
|
||||||
input logic [P.NE-1:0] Ze, // exponent of Z
|
input logic [P.NE-1:0] Ze, // exponent of Z
|
||||||
input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
|
input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
|
||||||
input logic [P.NE+1:0] Pe, // product's exponet
|
input logic [P.NE+1:0] Pe, // product's exponet
|
||||||
input logic [2*P.NF+1:0] Pm, // the product's mantissa
|
input logic [2*P.NF+1:0] Pm, // the product's mantissa
|
||||||
input logic InvA, // invert the aligned addend
|
input logic InvA, // invert the aligned addend
|
||||||
input logic KillProd, // should the product be set to 0
|
input logic KillProd, // should the product be set to 0
|
||||||
input logic ASticky, // Alighed addend's sticky bit
|
input logic ASticky, // Alighed addend's sticky bit
|
||||||
output logic [3*P.NF+3:0] AmInv, // aligned addend possibly inverted
|
output logic [3*P.NF+3:0] AmInv, // aligned addend possibly inverted
|
||||||
output logic [2*P.NF+1:0] PmKilled, // the product's mantissa possibly killed
|
output logic [2*P.NF+1:0] PmKilled, // the product's mantissa possibly killed
|
||||||
output logic Ss, // sum's sign
|
output logic Ss, // sum's sign
|
||||||
output logic [P.NE+1:0] Se, // sum's exponent
|
output logic [P.NE+1:0] Se, // sum's exponent
|
||||||
output logic [3*P.NF+3:0] Sm // the positive sum
|
output logic [3*P.NF+3:0] Sm // the positive sum
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum
|
logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum
|
||||||
logic NegSum; // was the sum negitive
|
logic NegSum; // was the sum negitive
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
// Addition
|
// Addition
|
||||||
|
Loading…
Reference in New Issue
Block a user