From b8570c4bef0ffab6342613b9f2167d10e2ab8569 Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Sun, 30 Jul 2023 16:59:27 -0700 Subject: [PATCH] Fixed spacing --- src/fpu/fma/fmaadd.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 52a2bf6cf..3d7dbbd81 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -29,21 +29,21 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( input logic [3*P.NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1) input logic [P.NE-1:0] Ze, // exponent of Z - input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations) + input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations) input logic [P.NE+1:0] Pe, // product's exponet input logic [2*P.NF+1:0] Pm, // the product's mantissa - input logic InvA, // invert the aligned addend - input logic KillProd, // should the product be set to 0 - input logic ASticky, // Alighed addend's sticky bit + input logic InvA, // invert the aligned addend + input logic KillProd, // should the product be set to 0 + input logic ASticky, // Alighed addend's sticky bit output logic [3*P.NF+3:0] AmInv, // aligned addend possibly inverted output logic [2*P.NF+1:0] PmKilled, // the product's mantissa possibly killed - output logic Ss, // sum's sign + output logic Ss, // sum's sign output logic [P.NE+1:0] Se, // sum's exponent output logic [3*P.NF+3:0] Sm // the positive sum ); logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum - logic NegSum; // was the sum negitive + logic NegSum; // was the sum negitive /////////////////////////////////////////////////////////////////////////////// // Addition