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Merge branch 'openhwgroup:main' into bitmanip_muxchange

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This commit is contained in:
Kevin Kim 2023-03-24 11:54:50 -07:00 committed by GitHub
commit b8349d480d
8 changed files with 24 additions and 32 deletions
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21
testbench/tests.vh
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@ -1852,7 +1852,6 @@ string arch64zbs[] = '{
string wally64priv[] = '{
`WALLYTEST,
// "rv64i_m/privilege/src/BUG66",
"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
"rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
"rv64i_m/privilege/src/WALLY-mie-01.S",
@ -1863,15 +1862,15 @@ string arch64zbs[] = '{
"rv64i_m/privilege/src/WALLY-mtvec-01.S",
"rv64i_m/privilege/src/WALLY-pma-01.S",
"rv64i_m/privilege/src/WALLY-pmp-01.S",
// "rv64i_m/privilege/src/WALLY-sie-01.S",
"rv64i_m/privilege/src/WALLY-sie-01.S",
"rv64i_m/privilege/src/WALLY-status-mie-01.S",
// "rv64i_m/privilege/src/WALLY-status-sie-01.S",
"rv64i_m/privilege/src/WALLY-status-sie-01.S",
"rv64i_m/privilege/src/WALLY-status-tw-01.S",
"rv64i_m/privilege/src/WALLY-status-tvm-01.S",
"rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S",
// "rv64i_m/privilege/src/WALLY-stvec-01.S",
// "rv64i_m/privilege/src/WALLY-trap-01.S",
// "rv64i_m/privilege/src/WALLY-trap-s-01.S",
"rv64i_m/privilege/src/WALLY-stvec-01.S",
"rv64i_m/privilege/src/WALLY-trap-01.S",
"rv64i_m/privilege/src/WALLY-trap-s-01.S",
"rv64i_m/privilege/src/WALLY-trap-sret-01.S",
"rv64i_m/privilege/src/WALLY-trap-u-01.S",
"rv64i_m/privilege/src/WALLY-wfi-01.S",
@ -1951,15 +1950,15 @@ string arch64zbs[] = '{
"rv32i_m/privilege/src/WALLY-mtvec-01.S",
"rv32i_m/privilege/src/WALLY-pma-01.S",
"rv32i_m/privilege/src/WALLY-pmp-01.S",
// "rv32i_m/privilege/src/WALLY-sie-01.S",
"rv32i_m/privilege/src/WALLY-sie-01.S",
"rv32i_m/privilege/src/WALLY-status-mie-01.S",
// "rv32i_m/privilege/src/WALLY-status-sie-01.S",
"rv32i_m/privilege/src/WALLY-status-sie-01.S",
"rv32i_m/privilege/src/WALLY-status-tw-01.S",
"rv32i_m/privilege/src/WALLY-status-tvm-01.S",
"rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S",
// "rv32i_m/privilege/src/WALLY-stvec-01.S",
// "rv32i_m/privilege/src/WALLY-trap-01.S",
// "rv32i_m/privilege/src/WALLY-trap-s-01.S",
"rv32i_m/privilege/src/WALLY-stvec-01.S",
"rv32i_m/privilege/src/WALLY-trap-01.S",
"rv32i_m/privilege/src/WALLY-trap-s-01.S",
"rv32i_m/privilege/src/WALLY-trap-sret-01.S",
"rv32i_m/privilege/src/WALLY-trap-u-01.S",
"rv32i_m/privilege/src/WALLY-wfi-01.S",

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -29,10 +29,6 @@
00000008 # scause from U mode ecall
00000000 # stval of ecall (*** defined to be zero for now)
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
0007ec01 # value to indicate successful vectoring on s soft interrupt
80000001 # scause value from s soft interrupt
00000000 # stval for ssoft interrupt (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt
80000003 # scause value from m soft interrupt
00000000 # stval for msoft interrupt (0x0)

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
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@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
//jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -60,14 +60,6 @@
00000000
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec01 # value to indicate successful vectoring on s soft interrupt
00000000
00000001 # scause value from s soft interrupt
80000000
00000000 # stval for ssoft interrupt (0x0)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec03 # value to indicate successful vectoring on m soft interrupt
00000000
00000003 # scause value from m soft interrupt

5
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
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@ -162,6 +162,11 @@ cause_s_soft_interrupt:
csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
ret
cause_s_soft_from_m_interrupt:
li t3, 0x2
csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
ret
cause_m_ext_interrupt:
// ========== Configure PLIC ==========
li a3, 0x40

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
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@ -49,7 +49,7 @@ jal cause_s_soft_interrupt // only cause one interrupt since we just want to tes
GOTO_M_MODE
jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
jal cause_s_soft_from_m_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
GOTO_U_MODE // Should cause software interrupt to fire off.

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
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@ -50,7 +50,7 @@ GOTO_S_MODE // Causes U mode ecall
GOTO_M_MODE // Causes S mode ecall
jal cause_s_soft_interrupt
jal cause_s_soft_from_m_interrupt
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
@ -72,7 +72,7 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall // M mode ecall
jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
jal cause_s_soft_interrupt // S Mode Interrupts Ignored in M mode. sip writeable when mideleg = 1
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
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@ -56,12 +56,12 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
//jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt