mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added function tracking to linux test bench.
This commit is contained in:
Ross Thompson
parent
bb3e94d68a
commit
b7972eafeb
@ -13,41 +13,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -265,7 +265,6 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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@ -362,28 +361,26 @@ add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/du
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add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
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add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
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add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
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add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
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add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
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add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
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add wave -noupdate -expand -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
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add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
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add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
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add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
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add wave -noupdate -expand -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
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add wave -noupdate -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
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add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
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add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
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add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
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add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
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add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
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add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
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add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
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@ -452,46 +449,35 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate -expand -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/checkInstrM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
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add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/ExpectedPCM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
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add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/line
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/line
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add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/textM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
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add wave -noupdate -expand -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW
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add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/checkInstrW
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
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add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/ExpectedPCW
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
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add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/TrapW
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
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add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/textW
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
|
||||||
add wave -noupdate /testbench/dut/hart/priv/csr/CSRReadValW
|
add wave -noupdate /testbench/FunctionName/FunctionAddr
|
||||||
add wave -noupdate /testbench/dut/hart/priv/csr/CSRReadValM
|
add wave -noupdate /testbench/FunctionName/FunctionName
|
||||||
add wave -noupdate /testbench/dut/hart/priv/TimerIntM
|
add wave -noupdate /testbench/FunctionName/ProgramAddrMapFile
|
||||||
add wave -noupdate /testbench/dut/hart/priv/ExtIntM
|
add wave -noupdate /testbench/FunctionName/ProgramLabelMapFile
|
||||||
add wave -noupdate /testbench/dut/hart/priv/SwIntM
|
|
||||||
add wave -noupdate /testbench/ExpectedIntType
|
|
||||||
add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/csri/IntInM
|
|
||||||
add wave -noupdate /testbench/dut/hart/priv/trap/PendingIntsM
|
|
||||||
add wave -noupdate /testbench/NumCSRM
|
|
||||||
add wave -noupdate /testbench/NumCSRW
|
|
||||||
add wave -noupdate /testbench/NumCSRPostWIndex
|
|
||||||
add wave -noupdate /testbench/ExpectedCSRArrayM
|
|
||||||
add wave -noupdate /testbench/ExpectedCSRArrayW
|
|
||||||
add wave -noupdate /testbench/ExpectedCSRArrayValueM
|
|
||||||
add wave -noupdate /testbench/ExpectedCSRArrayValueW
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 6} {161370956 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {39985218 ns} 0} {{Cursor 23} {8229603 ns} 0}
|
WaveRestoreCursors {{Cursor 6} {161370956 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {39985218 ns} 0} {{Cursor 23} {8750281 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 4
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 354
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
configure wave -signalnamewidth 1
|
configure wave -signalnamewidth 1
|
||||||
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
||||||
@ -504,4 +490,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {161370843 ns} {161371387 ns}
|
WaveRestoreZoom {0 ns} {9232357 ns}
|
||||||
|
|||||||
@ -85,7 +85,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
|
|||||||
end else if( array[mid] > pc) begin
|
end else if( array[mid] > pc) begin
|
||||||
right = mid -1;
|
right = mid -1;
|
||||||
end else begin
|
end else begin
|
||||||
$display("Critical Error in FunctionName. PC, %x not found.", pc);
|
//$display("Critical Error in FunctionName. PC, %x not found.", pc);
|
||||||
return;
|
return;
|
||||||
//$stop();
|
//$stop();
|
||||||
end
|
end
|
||||||
|
|||||||
@ -33,6 +33,8 @@ module testbench();
|
|||||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim
|
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim
|
||||||
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
||||||
|
|
||||||
|
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
///////////////////////////////////// DUT /////////////////////////////////////
|
///////////////////////////////////// DUT /////////////////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
@ -571,9 +573,17 @@ module testbench();
|
|||||||
end // always @ (negedge clk)
|
end // always @ (negedge clk)
|
||||||
|
|
||||||
|
|
||||||
|
// track the current function
|
||||||
|
FunctionName FunctionName(.reset(reset),
|
||||||
|
.clk(clk),
|
||||||
|
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||||
|
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
//////////////////////////////// Testbench Core ///////////////////////////////
|
//////////////////////////////// Testbench Core ///////////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// --------------
|
// --------------
|
||||||
// Initialization
|
// Initialization
|
||||||
// --------------
|
// --------------
|
||||||
@ -588,6 +598,8 @@ module testbench();
|
|||||||
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||||
|
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
|
||||||
|
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
|
||||||
end
|
end
|
||||||
|
|
||||||
// -------
|
// -------
|
||||||
@ -599,7 +611,6 @@ module testbench();
|
|||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
///////////////////////////////// Miscellaneous ///////////////////////////////
|
///////////////////////////////// Miscellaneous ///////////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user