diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv
index fb3d25adc..f896b506b 100644
--- a/src/lsu/dtim.sv
+++ b/src/lsu/dtim.sv
@@ -28,14 +28,17 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module dtim import cvw::*;  #(parameter cvw_t P) (
-  input logic                 clk, 
+  input logic                 clk, reset,
   input logic                 FlushW,        
   input logic                 ce,            // Chip Enable.  0: Holds ReadDataWordM
   input logic [1:0]           MemRWM,        // Read/Write control
+  input logic [1:0]           MemRWE,        // Read/Write control
   input logic [P.PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
   input logic [P.LLEN-1:0]    WriteDataM,    // Write data from IEU
   input logic [P.LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
-  output logic [P.LLEN-1:0]   ReadDataWordM  // Read data before subword selection
+  output logic [P.LLEN-1:0]   ReadDataWordM, // Read data before subword selection
+  output logic                DTIMStall,
+  output logic                DTIMSelWrite
   );
 
   logic                       we;
@@ -47,8 +50,16 @@ module dtim import cvw::*;  #(parameter cvw_t P) (
   localparam ADDR_WDITH = $clog2(DEPTH);
   localparam OFFSET     = $clog2(LLENBYTES);
 
-  assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
+  logic                       DTIMStallHazard, DTIMStallHazardD;
+  
+  assign DTIMStallHazard = MemRWM[0] & MemRWE[1];
+  flopr #(1) DTIMStallReg(clk, reset, DTIMStallHazard, DTIMStallHazardD);
+  assign DTIMStall = DTIMStallHazard & ~DTIMStallHazardD;
+
+  assign DTIMSelWrite = MemRWM[0] & ~(DTIMStallHazard & ~DTIMStall);
+  
+  assign we = DTIMSelWrite & ~FlushW;  // have to ignore write if Trap.
 
   ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(DEPTH), .WIDTH(P.LLEN)) 
-    ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
+    ram(.clk, .ce(ce | DTIMSelWrite), .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 432c7ce79..3207954f1 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -150,6 +150,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic                  IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
   logic                  SelDTIM;                                // Select DTIM rather than bus or D$
   logic [P.XLEN-1:0]     WriteDataZM;
+  logic                  DTIMStall;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M
@@ -219,7 +220,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   // the trap module.
   assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
   assign GatedStallW = StallW & ~SelHPTW;
-  assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall;
+  assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall | DTIMStall;
   assign LSUStallM = CacheBusHPWTStall | SpillStallM;
 
   /////////////////////////////////////////////////////////////////////////////////////////////
@@ -268,17 +269,20 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   if (P.DTIM_SUPPORTED) begin : dtim
     logic [P.PA_BITS-1:0] DTIMAdr;
     logic [1:0]           DTIMMemRWM;
+    logic                 DTIMSelWrite;
     
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
-    mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
+    mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], DTIMSelWrite, DTIMAdr);
     assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
     // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
     // **** create config to support DTIM with floating point.
     // Add support for cboz
-    dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
+    dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWE(MemRWE), // *** update when you update the cache RWE
+              .MemRWM(DTIMMemRWM),
               .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), 
-              .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
+              .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM), .DTIMStall, .DTIMSelWrite);
   end else begin
+    assign DTIMStall = '0;
   end
   if (P.BUS_SUPPORTED) begin : bus              
     if(P.DCACHE_SUPPORTED) begin : dcache