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https://github.com/openhwgroup/cvw
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Replaced separate PageTypeF and PageTypeM with common PageType
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@ -68,7 +68,7 @@ module ifu (
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PageTableEntryF,
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input logic [1:0] PageTypeF,
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input logic [1:0] PageType,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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@ -117,7 +117,7 @@ module ifu (
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immu(.Address(PCF),
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.Size(2'b10),
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.PTE(PageTableEntryF),
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.PageTypeWriteVal(PageTypeF),
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.PageTypeWriteVal(PageType),
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.TLBWrite(ITLBWriteF),
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.TLBFlush(ITLBFlushF),
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.PhysicalAddress(PCPFmmu),
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@ -82,7 +82,7 @@ module lsu
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input logic [`XLEN-1:0] PCF,
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input logic ITLBMissF,
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output logic [`XLEN-1:0] PageTableEntryF,
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output logic [1:0] PageTypeF,
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output logic [1:0] PageType,
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output logic ITLBWriteF,
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output logic WalkerInstrPageFaultF,
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output logic WalkerLoadPageFaultM,
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@ -119,7 +119,6 @@ module lsu
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logic DTLBMissM;
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logic [`XLEN-1:0] PageTableEntryM;
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logic [1:0] PageTypeM;
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logic DTLBWriteM;
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logic [`XLEN-1:0] HPTWReadPTE;
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logic MMUReady;
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@ -161,8 +160,7 @@ module lsu
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.MemRWM(MemRWM),
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.PageTableEntryF(PageTableEntryF),
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.PageTableEntryM(PageTableEntryM),
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.PageTypeF(PageTypeF),
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.PageTypeM(PageTypeM),
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.PageType,
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.ITLBWriteF(ITLBWriteF),
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.DTLBWriteM(DTLBWriteM),
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.HPTWReadPTE(HPTWReadPTE),
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@ -223,7 +221,7 @@ module lsu
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dmmu(.Address(MemAdrMtoDCache),
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.Size(Funct3MtoDCache[1:0]),
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.PTE(PageTableEntryM),
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.PageTypeWriteVal(PageTypeM),
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.PageTypeWriteVal(PageType),
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.TLBWrite(DTLBWriteM),
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.TLBFlush(DTLBFlushM),
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.PhysicalAddress(MemPAdrM),
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@ -47,7 +47,7 @@ module pagetablewalker
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// Outputs to the TLBs (PTEs to write)
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output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
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output logic [1:0] PageTypeF, PageTypeM,
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output logic [1:0] PageType,
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output logic ITLBWriteF, DTLBWriteM,
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output logic SelPTW,
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@ -92,7 +92,6 @@ module pagetablewalker
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// Outputs of walker
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logic [`XLEN-1:0] PageTableEntry;
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logic [1:0] PageType;
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logic StartWalk;
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logic EndWalk;
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@ -170,9 +169,6 @@ module pagetablewalker
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// Assign specific outputs to general outputs
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assign PageTableEntryF = PageTableEntry;
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assign PageTableEntryM = PageTableEntry;
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assign PageTypeF = PageType;
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assign PageTypeM = PageType;
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// generate
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if (`XLEN == 32) begin
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@ -182,10 +178,6 @@ module pagetablewalker
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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/* -----\/----- EXCLUDED -----\/-----
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assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
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-----/\----- EXCLUDED -----/\----- */
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// State transition logic
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always_comb begin
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PRegEn = 1'b0;
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@ -118,7 +118,7 @@ module wallypipelinedhart
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logic [1:0] STATUS_MPP;
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logic [1:0] PrivilegeModeW;
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logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
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logic [1:0] PageTypeF, PageTypeM;
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logic [1:0] PageType;
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// PMA checker signals
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logic DSquashBusAccessM, ISquashBusAccessF;
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@ -226,7 +226,7 @@ module wallypipelinedhart
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.PCF(PCF),
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.ITLBMissF(ITLBMissF),
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.PageTableEntryF(PageTableEntryF),
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.PageTypeF(PageTypeF),
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.PageType,
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.ITLBWriteF(ITLBWriteF),
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.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
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.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
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