From b65788d165a9ed0b2e97a6985249f256139fbd79 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 17 Jul 2021 02:31:23 -0400
Subject: [PATCH] Replaced separate PageTypeF and PageTypeM with common
 PageType

---
 wally-pipelined/src/ifu/ifu.sv                  |  4 ++--
 wally-pipelined/src/lsu/lsu.sv                  |  8 +++-----
 wally-pipelined/src/mmu/pagetablewalker.sv      | 10 +---------
 wally-pipelined/src/wally/wallypipelinedhart.sv |  4 ++--
 4 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index a0728a1ad..9c2e92915 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -68,7 +68,7 @@ module ifu (
   // mmu management
   input logic [1:0] 	      PrivilegeModeW,
   input logic [`XLEN-1:0]     PageTableEntryF,
-  input logic [1:0] 	      PageTypeF,
+  input logic [1:0] 	      PageType,
   input logic [`XLEN-1:0]     SATP_REGW,
   input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input logic  [1:0]       STATUS_MPP,
@@ -117,7 +117,7 @@ module ifu (
   immu(.Address(PCF),
        .Size(2'b10),
        .PTE(PageTableEntryF),
-       .PageTypeWriteVal(PageTypeF),
+       .PageTypeWriteVal(PageType),
        .TLBWrite(ITLBWriteF),
        .TLBFlush(ITLBFlushF),
        .PhysicalAddress(PCPFmmu),
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index cf11e7178..46f174a97 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -82,7 +82,7 @@ module lsu
    input logic [`XLEN-1:0]     PCF,
    input logic 		       ITLBMissF,
    output logic [`XLEN-1:0]    PageTableEntryF,
-   output logic [1:0] 	       PageTypeF,
+   output logic [1:0] 	       PageType,
    output logic 	       ITLBWriteF,
    output logic 	       WalkerInstrPageFaultF,
    output logic 	       WalkerLoadPageFaultM,
@@ -119,7 +119,6 @@ module lsu
  
   logic 		       DTLBMissM;
   logic [`XLEN-1:0] 	       PageTableEntryM;
-  logic [1:0] 		       PageTypeM;
   logic 		       DTLBWriteM;
   logic [`XLEN-1:0] 	       HPTWReadPTE;
   logic 		       MMUReady;
@@ -161,8 +160,7 @@ module lsu
 				  .MemRWM(MemRWM),
 				  .PageTableEntryF(PageTableEntryF),
 				  .PageTableEntryM(PageTableEntryM),
-				  .PageTypeF(PageTypeF),
-				  .PageTypeM(PageTypeM),
+				  .PageType,
 				  .ITLBWriteF(ITLBWriteF),
 				  .DTLBWriteM(DTLBWriteM),
 				  .HPTWReadPTE(HPTWReadPTE),
@@ -223,7 +221,7 @@ module lsu
   dmmu(.Address(MemAdrMtoDCache),
        .Size(Funct3MtoDCache[1:0]),
        .PTE(PageTableEntryM),
-       .PageTypeWriteVal(PageTypeM),
+       .PageTypeWriteVal(PageType),
        .TLBWrite(DTLBWriteM),
        .TLBFlush(DTLBFlushM),
        .PhysicalAddress(MemPAdrM),
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index a41f5ca0d..ea4c4de3f 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -47,7 +47,7 @@ module pagetablewalker
 
    // Outputs to the TLBs (PTEs to write)
    output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
-   output logic [1:0]	    PageTypeF, PageTypeM,
+   output logic [1:0]	    PageType,
    output logic		    ITLBWriteF, DTLBWriteM,
    output logic 	    SelPTW,
 
@@ -92,7 +92,6 @@ module pagetablewalker
 
       // Outputs of walker
       logic [`XLEN-1:0]		    PageTableEntry;
-      logic [1:0]		    PageType;
       logic			    StartWalk;
       logic			    EndWalk;
 
@@ -170,9 +169,6 @@ module pagetablewalker
       // Assign specific outputs to general outputs
       assign PageTableEntryF = PageTableEntry;
       assign PageTableEntryM = PageTableEntry;
-      assign PageTypeF = PageType;
-      assign PageTypeM = PageType;
-
 
       //      generate
       if (`XLEN == 32) begin
@@ -182,10 +178,6 @@ module pagetablewalker
 
 	flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
 	
-	/* -----\/----- EXCLUDED -----\/-----
-	 assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
-	 -----/\----- EXCLUDED -----/\----- */
-
 	// State transition logic
 	always_comb begin
 	  PRegEn = 1'b0;
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 3560cae51..fc71e6c1b 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -118,7 +118,7 @@ module wallypipelinedhart
   logic  [1:0]       STATUS_MPP;
   logic [1:0] 		    PrivilegeModeW;
   logic [`XLEN-1:0] 	    PageTableEntryF, PageTableEntryM;
-  logic [1:0] 		    PageTypeF, PageTypeM;
+  logic [1:0] 		    PageType;
 
   // PMA checker signals
   logic 		    DSquashBusAccessM, ISquashBusAccessF;
@@ -226,7 +226,7 @@ module wallypipelinedhart
 	  .PCF(PCF),
 	  .ITLBMissF(ITLBMissF),
 	  .PageTableEntryF(PageTableEntryF),
-	  .PageTypeF(PageTypeF),
+	  .PageType,
 	  .ITLBWriteF(ITLBWriteF),
 	  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 	  .WalkerLoadPageFaultM(WalkerLoadPageFaultM),