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Replaced separate PageTypeF and PageTypeM with common PageType

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This commit is contained in:
David Harris 2021-07-17 02:31:23 -04:00
parent dac22d5016
commit b65788d165
4 changed files with 8 additions and 18 deletions
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4
wally-pipelined/src/ifu/ifu.sv
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@ -68,7 +68,7 @@ module ifu (
// mmu management // mmu management
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] PageTableEntryF, input logic [`XLEN-1:0] PageTableEntryF,
input logic [1:0] PageTypeF, input logic [1:0] PageType,
input logic [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
@ -117,7 +117,7 @@ module ifu (
immu(.Address(PCF), immu(.Address(PCF),
.Size(2'b10), .Size(2'b10),
.PTE(PageTableEntryF), .PTE(PageTableEntryF),
.PageTypeWriteVal(PageTypeF), .PageTypeWriteVal(PageType),
.TLBWrite(ITLBWriteF), .TLBWrite(ITLBWriteF),
.TLBFlush(ITLBFlushF), .TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPFmmu), .PhysicalAddress(PCPFmmu),

8
wally-pipelined/src/lsu/lsu.sv
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@ -82,7 +82,7 @@ module lsu
input logic [`XLEN-1:0] PCF, input logic [`XLEN-1:0] PCF,
input logic ITLBMissF, input logic ITLBMissF,
output logic [`XLEN-1:0] PageTableEntryF, output logic [`XLEN-1:0] PageTableEntryF,
output logic [1:0] PageTypeF, output logic [1:0] PageType,
output logic ITLBWriteF, output logic ITLBWriteF,
output logic WalkerInstrPageFaultF, output logic WalkerInstrPageFaultF,
output logic WalkerLoadPageFaultM, output logic WalkerLoadPageFaultM,
@ -119,7 +119,6 @@ module lsu
logic DTLBMissM; logic DTLBMissM;
logic [`XLEN-1:0] PageTableEntryM; logic [`XLEN-1:0] PageTableEntryM;
logic [1:0] PageTypeM;
logic DTLBWriteM; logic DTLBWriteM;
logic [`XLEN-1:0] HPTWReadPTE; logic [`XLEN-1:0] HPTWReadPTE;
logic MMUReady; logic MMUReady;
@ -161,8 +160,7 @@ module lsu
.MemRWM(MemRWM), .MemRWM(MemRWM),
.PageTableEntryF(PageTableEntryF), .PageTableEntryF(PageTableEntryF),
.PageTableEntryM(PageTableEntryM), .PageTableEntryM(PageTableEntryM),
.PageTypeF(PageTypeF), .PageType,
.PageTypeM(PageTypeM),
.ITLBWriteF(ITLBWriteF), .ITLBWriteF(ITLBWriteF),
.DTLBWriteM(DTLBWriteM), .DTLBWriteM(DTLBWriteM),
.HPTWReadPTE(HPTWReadPTE), .HPTWReadPTE(HPTWReadPTE),
@ -223,7 +221,7 @@ module lsu
dmmu(.Address(MemAdrMtoDCache), dmmu(.Address(MemAdrMtoDCache),
.Size(Funct3MtoDCache[1:0]), .Size(Funct3MtoDCache[1:0]),
.PTE(PageTableEntryM), .PTE(PageTableEntryM),
.PageTypeWriteVal(PageTypeM), .PageTypeWriteVal(PageType),
.TLBWrite(DTLBWriteM), .TLBWrite(DTLBWriteM),
.TLBFlush(DTLBFlushM), .TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM), .PhysicalAddress(MemPAdrM),

10
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -47,7 +47,7 @@ module pagetablewalker
// Outputs to the TLBs (PTEs to write) // Outputs to the TLBs (PTEs to write)
output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM, output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
output logic [1:0] PageTypeF, PageTypeM, output logic [1:0] PageType,
output logic ITLBWriteF, DTLBWriteM, output logic ITLBWriteF, DTLBWriteM,
output logic SelPTW, output logic SelPTW,
@ -92,7 +92,6 @@ module pagetablewalker
// Outputs of walker // Outputs of walker
logic [`XLEN-1:0] PageTableEntry; logic [`XLEN-1:0] PageTableEntry;
logic [1:0] PageType;
logic StartWalk; logic StartWalk;
logic EndWalk; logic EndWalk;
@ -170,9 +169,6 @@ module pagetablewalker
// Assign specific outputs to general outputs // Assign specific outputs to general outputs
assign PageTableEntryF = PageTableEntry; assign PageTableEntryF = PageTableEntry;
assign PageTableEntryM = PageTableEntry; assign PageTableEntryM = PageTableEntry;
assign PageTypeF = PageType;
assign PageTypeM = PageType;
// generate // generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
@ -182,10 +178,6 @@ module pagetablewalker
flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
/* -----\/----- EXCLUDED -----\/-----
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
-----/\----- EXCLUDED -----/\----- */
// State transition logic // State transition logic
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;

4
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -118,7 +118,7 @@ module wallypipelinedhart
logic [1:0] STATUS_MPP; logic [1:0] STATUS_MPP;
logic [1:0] PrivilegeModeW; logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM; logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
logic [1:0] PageTypeF, PageTypeM; logic [1:0] PageType;
// PMA checker signals // PMA checker signals
logic DSquashBusAccessM, ISquashBusAccessF; logic DSquashBusAccessM, ISquashBusAccessF;
@ -226,7 +226,7 @@ module wallypipelinedhart
.PCF(PCF), .PCF(PCF),
.ITLBMissF(ITLBMissF), .ITLBMissF(ITLBMissF),
.PageTableEntryF(PageTableEntryF), .PageTableEntryF(PageTableEntryF),
.PageTypeF(PageTypeF), .PageType,
.ITLBWriteF(ITLBWriteF), .ITLBWriteF(ITLBWriteF),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
.WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerLoadPageFaultM(WalkerLoadPageFaultM),