Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Updated debug2 ila signal names.

Browse Source
This commit is contained in:
Ross Thompson 2022-01-28 11:43:49 -06:00
parent 1bb8d36308
commit b621eb78fb
2 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/constraints/debug2.xdc
View File

@ -282,7 +282,7 @@ connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/priv.p
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StorePageFaultM ]]
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]

6
fpga/generator/xlnx_ahblite_axi_bridge.tcl
View File

@ -1,9 +1,15 @@
#set partNumber $::env(XILINX_PART)
#set boardNmae $::env(XILINX_BOARD)
# vcu118 board
set partNumber xcvu9p-flga2104-2L-e
set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_ahblite_axi_bridge
create_project $ipName . -force -part $partNumber