From b621eb78fbd5032e09bb7a4d6e7e929230dbe09d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 28 Jan 2022 11:43:49 -0600 Subject: [PATCH] Updated debug2 ila signal names. --- fpga/constraints/debug2.xdc | 2 +- fpga/generator/xlnx_ahblite_axi_bridge.tcl | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 48046d1df..63fa17a40 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -282,7 +282,7 @@ connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/priv.p create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe66] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] -connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StorePageFaultM ]] +connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe67] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] diff --git a/fpga/generator/xlnx_ahblite_axi_bridge.tcl b/fpga/generator/xlnx_ahblite_axi_bridge.tcl index ab3839820..317a62c09 100644 --- a/fpga/generator/xlnx_ahblite_axi_bridge.tcl +++ b/fpga/generator/xlnx_ahblite_axi_bridge.tcl @@ -1,9 +1,15 @@ #set partNumber $::env(XILINX_PART) #set boardNmae $::env(XILINX_BOARD) + +# vcu118 board set partNumber xcvu9p-flga2104-2L-e set boardName xilinx.com:vcu118:part0:2.4 +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + set ipName xlnx_ahblite_axi_bridge create_project $ipName . -force -part $partNumber