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Reset STIMECMP to 0 to agree with ImperasDV

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This commit is contained in:
David Harris 2023-11-21 13:43:51 -08:00
parent 2b2016271a
commit b5f79c44f9
1 changed files with 3 additions and 3 deletions
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6
src/privileged/csrs.sv
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@ -111,10 +111,10 @@ module csrs import cvw::*; #(parameter cvw_t P) (
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
if (P.SSTC_SUPPORTED) begin : sstc if (P.SSTC_SUPPORTED) begin : sstc
if (P.XLEN == 64) begin : sstc64 if (P.XLEN == 64) begin : sstc64
flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW);
end else begin : sstc32 end else begin : sstc32
flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]);
flopenl #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); flopenr #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]);
end end
end else assign STIMECMP_REGW = 0; end else assign STIMECMP_REGW = 0;