From b5f79c44f957aa74c62dadc3ce054a1be2fa1f2d Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 21 Nov 2023 13:43:51 -0800 Subject: [PATCH] Reset STIMECMP to 0 to agree with ImperasDV --- src/privileged/csrs.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 3d914aef3..da8ab48bf 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -111,10 +111,10 @@ module csrs import cvw::*; #(parameter cvw_t P) ( flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (P.SSTC_SUPPORTED) begin : sstc if (P.XLEN == 64) begin : sstc64 - flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); + flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW); end else begin : sstc32 - flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); - flopenl #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); + flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]); + flopenr #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]); end end else assign STIMECMP_REGW = 0;